| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 671 return HVC.getFullValue(HVC.getBoolTy(HVC.length(VecTy))); in getMask()
672 return HVC.getFullValue(HVC.getBoolTy()); in getMask()
761 assert(HVC.getSizeOf(ValTy, HVC.Alloc) % Alignment == 0); in createPredicatedLoad()
777 if (HVC.isZero(Mask) || HVC.isUndef(Val) || HVC.isUndef(Mask)) in createStore()
837 assert(HVC.getSizeOf(Val, HVC.Alloc) % Alignment == 0); in createPredicatedStore()
1110 auto *True = HVC.getFullValue(HVC.getBoolTy(ScLen)); in realignLoadGroup()
1383 if (HVC.isUndef(Val) || HVC.isZero(Mask)) in realignStoreGroup()
1950 CarryIn = HVC.getNullValue(HVC.getBoolTy(HVC.length(VecTy))); in createAddCarry()
2002 return HVC.vshuff(Builder, HVC.sublo(Builder, P), HVC.subhi(Builder, P)); in createMul16()
2007 Type *HvxI16Ty = HVC.getHvxTy(HVC.getIntTy(16), /*Pair=*/false); in createMulH16()
[all …]
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/arm/firmware/ |
| H A D | linaro,optee-tz.txt | 20 "hvc" : HVC #0, with the register assignments specified
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| H A D | linaro,optee-tz.yaml | 41 HVC #0, register assignments
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| H A D | sdei.txt | 34 * "hvc" : HVC #0, with the register assignments specified in this
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.txt | 20 - "hvc" : HVC #0, following the SMCCC
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| H A D | xlnx,zynqmp-firmware.yaml | 34 - "hvc" : HVC #0, following the SMCCC
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | xlnx,zynqmp-ipi-mailbox.yaml | 47 - "hvc" : HVC #0, following the SMCCC
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/arm/ |
| H A D | psci.yaml | 70 # HVC #0, with the register assignments specified in this binding.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | arm,scmi.yaml | 34 - description: SCMI compliant firmware with ARM SMC/HVC transport
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 687 case ARM::HVC: in isIndirectCall()
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| H A D | ARMScheduleA57.td | 119 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
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| H A D | ARMInstrInfo.td | 2800 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2805 // Even though HVC isn't predicable, it's encoding includes a condition field.
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| H A D | ARMInstrThumb2.td | 4309 // Alias for HVC without the ".w" optional width specifier
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| /freebsd-14.2/contrib/file/magic/Magdir/ |
| H A D | console | 86 >0x11 string *NINTENDO-HVC* Famicom Disk System disk image:
93 1 string *NINTENDO-HVC* Famicom Disk System disk image:
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| H A D | AArch64SchedKryoDetails.td | 477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| H A D | AArch64InstrInfo.td | 2920 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 718 case ARM::HVC: { in checkDecodedInstruction()
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