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Searched refs:GPR_64 (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td209 GPR_64;
437 GPR_64 {
446 GPR_64 {
657 GPR_64;
659 GPR_64;
661 GPR_64;
663 GPR_64;
671 GPR_64;
841 GPR_64;
951 GPR_64;
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H A DMipsCondMov.td205 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
207 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
209 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
211 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
213 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
215 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
217 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
219 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
226 GPR_64;
228 GPR_64;
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H A DMips64r6InstrInfo.td168 def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
169 def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
171 def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
172 def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
173 def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
174 def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
175 def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
176 def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
177 def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64;
178 def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64;
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H A DMipsInstrFPU.td959 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
960 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
H A DMipsInstrInfo.td268 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86GenRegisterBankInfo.def58 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
H A DX86CallingConv.td43 list<Register> GPR_64 = [];
56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
129 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
134 CCAssignToReg<RC.GPR_64>>>,
208 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
213 CCAssignToReg<RC.GPR_64>>>,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6748 static const MCPhysReg GPR_64[] = {// 64-bit registers. in CC_AIX() local
6776 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6803 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6824 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6877 ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
7330 static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in LowerFormalArguments_AIX() local
7332 const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32); in LowerFormalArguments_AIX()
7342 IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass) in LowerFormalArguments_AIX()