Home
last modified time | relevance | path

Searched refs:GENMASK (Results 1 – 25 of 159) sorted by relevance

1234567

/freebsd-14.2/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac3_mac.h24 #define MT_RXD0_LENGTH GENMASK(15, 0)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
105 #define MT_PRXV_NSTS GENMASK(10, 7)
111 #define MT_PRXV_RCPI1 GENMASK(15, 8)
112 #define MT_PRXV_RCPI0 GENMASK(7, 0)
194 #define MT_TXD1_TID GENMASK(24, 21)
218 #define MT_TXD3_SEQ GENMASK(27, 16)
238 #define MT_TXD5_PID GENMASK(7, 0)
242 #define MT_TXD6_BW GENMASK(25, 22)
281 #define MT_TXS0_BW GENMASK(31, 29)
[all …]
H A Dmt76_connac2_mac.h37 #define MT_TX_FREE_COUNT GENMASK(12, 0)
43 #define MT_TX_FREE_RATE GENMASK(13, 0)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
54 #define MT_TXD1_TID GENMASK(22, 20)
60 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
66 #define MT_TXD2_FRAG GENMASK(15, 14)
82 #define MT_TXD3_SEQ GENMASK(27, 16)
100 #define MT_TXD5_PID GENMASK(7, 0)
105 #define MT_TXD6_SGI GENMASK(15, 14)
112 #define MT_TXD6_BW GENMASK(1, 0)
[all …]
H A Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
110 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
142 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
146 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
150 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
156 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
167 #define MT_US_CYC_CNT GENMASK(7, 0)
[all …]
H A Dmt792x_regs.h37 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
38 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
41 #define MT_IFS_EIFS GENMASK(8, 0)
42 #define MT_IFS_RIFS GENMASK(14, 10)
43 #define MT_IFS_SIFS GENMASK(22, 16)
44 #define MT_IFS_SLOT GENMASK(30, 24)
90 #define MT_ETBF_RX_FB_HE GENMASK(23, 16)
91 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
92 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
170 #define MT_WTBL_LMAC_ID GENMASK(14, 8)
[all …]
/freebsd-14.2/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
94 #define MT_RXV3_RCPI0 GENMASK(15, 8)
109 #define MT_RXV5_FOE GENMASK(18, 7)
117 #define MT_RXV6_NF2 GENMASK(23, 16)
118 #define MT_RXV6_NF1 GENMASK(15, 8)
119 #define MT_RXV6_NF0 GENMASK(7, 0)
141 #define MT_TXD1_TID GENMASK(22, 20)
181 #define MT_TXD5_PID GENMASK(7, 0)
192 #define MT_TXD6_BW GENMASK(9, 8)
[all …]
H A Dregs.h29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
108 #define MT_PSE_FRP_P0 GENMASK(2, 0)
109 #define MT_PSE_FRP_P1 GENMASK(5, 3)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
229 #define MT_AGG_BWCR_BW GENMASK(3, 2)
395 #define MT_IFS_EIFS GENMASK(8, 0)
396 #define MT_IFS_RIFS GENMASK(14, 10)
397 #define MT_IFS_SIFS GENMASK(22, 16)
[all …]
/freebsd-14.2/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
107 #define MT_RXV4_RCPI0 GENMASK(7, 0)
109 #define MT_RXV5_FOE GENMASK(11, 0)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
112 #define MT_RXV6_NF2 GENMASK(23, 16)
113 #define MT_RXV6_NF1 GENMASK(15, 8)
114 #define MT_RXV6_NF0 GENMASK(7, 0)
208 #define MT_TXD5_PID GENMASK(7, 0)
218 #define MT_TXD6_BW GENMASK(1, 0)
[all …]
H A Dregs.h46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
112 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
150 #define MT_MCU_CMD_ERROR_MASK (GENMASK(5, 1) | GENMASK(28, 24))
187 #define MT_PSE_SRC_CNT GENMASK(27, 16)
226 GENMASK(28, 20))
239 GENMASK(8, 1)
319 #define MT_IFS_EIFS GENMASK(8, 0)
320 #define MT_IFS_RIFS GENMASK(14, 10)
321 #define MT_IFS_SIFS GENMASK(22, 16)
[all …]
/freebsd-14.2/sys/contrib/dev/rtw89/
H A Dreg.h12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14)
108 #define B_AX_DBG_SEL0 GENMASK(7, 0)
127 #define B_AX_R_AX_BG GENMASK(1, 0)
204 #define PS_CPWM_STATE GENMASK(2, 0)
3719 #define RR_TM_VAL GENMASK(6, 1)
4193 #define B_DCFO GENMASK(7, 0)
4517 #define B_DPD_REF GENMASK(8, 0)
4913 #define B_ADDCK0 GENMASK(9, 8)
4927 #define B_DACK10 GENMASK(4, 1)
4931 #define B_DACK11 GENMASK(4, 1)
[all …]
H A Dtxrx.h10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7)
12 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0)
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
19 #define DATA_RATE_NSS_MASK_V1 GENMASK(7, 5)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
162 #define AX_RXD_BW_MASK GENMASK(31, 30)
191 #define AX_RXD_TYPE_MASK GENMASK(1, 0)
198 #define AX_RXD_TID_MASK GENMASK(11, 8)
202 #define AX_RXD_SEQ_MASK GENMASK(27, 16)
[all …]
H A Dfw.h545 GENMASK(8, 0)); in SET_CMC_TBL_DATARATE()
643 GENMASK(8, 0)); in SET_CMC_TBL_DATA_RTY_LOWEST_RATE()
699 GENMASK(5, 0)); in SET_CMC_TBL_DATA_TX_CNT_LMT()
776 GENMASK(7, 0)); in SET_CMC_TBL_MAX_AGG_NUM()
783 GENMASK(9, 8)); in SET_CMC_TBL_BA_BMAP()
825 GENMASK(2, 0)); in SET_CMC_TBL_MULTI_PORT_ID()
839 GENMASK(7, 4)); in SET_CMC_TBL_MBSSID()
944 GENMASK(8, 0)); in SET_CMC_TBL_RESP_REF_RATE()
1029 GENMASK(1, 0)); in SET_CMC_TBL_NOMINAL_PKT_PADDING_V1()
1036 GENMASK(3, 2)); in SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1()
[all …]
H A Dcam.h12 #define RTW89_BSSID_MATCH_ALL GENMASK(5, 0)
13 #define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0)
17 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)); in FWCMD_SET_ADDR_IDX()
22 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)); in FWCMD_SET_ADDR_OFFSET()
27 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)); in FWCMD_SET_ADDR_LEN()
37 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)); in FWCMD_SET_ADDR_NET_TYPE()
42 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3)); in FWCMD_SET_ADDR_BCN_HIT_COND()
47 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5)); in FWCMD_SET_ADDR_HIT_RULE()
57 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8)); in FWCMD_SET_ADDR_ADDR_MASK()
77 le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0)); in FWCMD_SET_ADDR_BSSID_CAM_IDX()
[all …]
/freebsd-14.2/sys/contrib/dev/athk/ath12k/
H A Dhal_desc.h11 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
13 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
14 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8)
15 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12)
569 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
570 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
571 #define HAL_TLV_USR_ID GENMASK(31, 26)
580 #define HAL_TLV_64_HDR_TAG GENMASK(9, 1)
581 #define HAL_TLV_64_HDR_LEN GENMASK(21, 10)
598 #define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28)
[all …]
H A Dhal_tx.h69 #define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16)
71 #define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21)
73 #define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0)
75 #define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21)
76 #define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4)
77 #define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19)
124 #define HAL_TX_Q_EXT_INFO0_FRAME_CTRL GENMASK(15, 0)
125 #define HAL_TX_Q_EXT_INFO0_QOS_CTRL GENMASK(31, 16)
172 #define HAL_TX_BANK_CONFIG_ENCAP_TYPE GENMASK(2, 1)
179 #define HAL_TX_BANK_CONFIG_MESH_EN GENMASK(13, 12)
[all …]
H A Dhal_rx.h29 le32_get_bits((__val), GENMASK(7, 0))
32 le32_get_bits((__val), GENMASK(15, 8))
35 le32_get_bits((__val), GENMASK(23, 16))
38 le32_get_bits((__val), GENMASK(31, 24))
298 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
301 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
310 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
311 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
317 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
457 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
[all …]
H A Drx_desc.h25 #define RX_MPDU_START_INFO0_REO_DEST_IND GENMASK(4, 0)
46 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
48 #define RX_MPDU_START_INFO2_MESH_STA GENMASK(9, 8)
51 #define RX_MPDU_START_INFO2_TID GENMASK(18, 15)
80 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)
93 #define RX_MPDU_START_INFO6_MPDU_LEN GENMASK(13, 0)
112 #define RX_MPDU_START_INFO7_VDEV_ID GENMASK(7, 0)
625 #define RX_MSDU_END_INFO4_TCP_FLAG GENMASK(8, 0)
631 #define RX_MSDU_END_INFO5_TID GENMASK(6, 3)
660 #define RX_MSDU_END_INFO8_KEY_ID GENMASK(7, 0)
[all …]
H A Ddp.h86 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
191 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0)
192 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
193 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
242 #define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0)
243 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
245 #define DP_REO_QREF_NUM GENMASK(31, 16)
402 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0)
1204 #define HTT_T2H_MSG_TYPE GENMASK(7, 0)
1348 #define HTT_TLV_TAG GENMASK(11, 0)
[all …]
/freebsd-14.2/sys/contrib/dev/athk/ath11k/
H A Dhal_desc.h10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
476 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
477 #define HAL_TLV_USR_ID GENMASK(31, 26)
487 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
1528 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)
1890 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
[all …]
H A Dhal_rx.h195 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
252 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
255 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
264 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
265 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
271 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
272 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
279 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
390 #define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0)
404 #define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
[all …]
H A Drx_desc.h28 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0)
29 #define RX_DESC_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2)
365 #define RX_MPDU_START_INFO2_ENC_TYPE GENMASK(5, 2)
370 #define RX_MPDU_START_INFO2_TID GENMASK(17, 14)
386 #define RX_MPDU_START_INFO5_KEY_ID GENMASK(7, 0)
465 #define RX_MPDU_START_INFO9_TID GENMASK(18, 15)
493 #define RX_MPDU_START_INFO12_KEY_ID GENMASK(7, 0)
801 #define RX_MSDU_START_INFO3_SGI GENMASK(14, 13)
1023 #define RX_MSDU_END_INFO1_KEY_ID GENMASK(7, 0)
1046 #define RX_MSDU_END_INFO3_TCP_FLAG GENMASK(8, 0)
[all …]
/freebsd-14.2/sys/contrib/dev/rtw88/
H A Drtw8822c.h180 #define XCAP_MASK GENMASK(6, 0)
188 #define BIT_ANT_PATH GENMASK(1, 0)
232 #define BIT_BBMODE GENMASK(2, 1)
255 #define BIT_SUBPAGE GENMASK(3, 0)
277 #define BIT_Q_GAIN GENMASK(11, 0)
291 #define BIT_DPD_CLK GENMASK(7, 4)
331 #define BIT_ANTSEG GENMASK(3, 0)
335 #define BIT_STOP_TX GENMASK(3, 0)
363 #define BIT_RXAGC GENMASK(9, 5)
364 #define BIT_TXAGC GENMASK(4, 0)
[all …]
H A Dfw.h89 #define RTW_H2C_W0_CMDID GENMASK(7, 0)
92 #define RTW_H2C_DEFAULT_PORT_W0_PORTID GENMASK(15, 8)
93 #define RTW_H2C_DEFAULT_PORT_W0_MACID GENMASK(23, 16)
437 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
439 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
441 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
443 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
445 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
450 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
454 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
[all …]
H A Drtw8723d.h158 #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)
180 #define BIT_MASK_RXBB_DFIR GENMASK(27, 24)
196 #define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)
197 #define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)
211 #define BIT_MASK_RXDSP GENMASK(28, 24)
240 #define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13)
252 #define BIT_MASK_CTX_TYPE GENMASK(6, 4)
283 #define BIT_MASK_RES_TX GENMASK(25, 16)
285 #define BIT_MASK_RES_TY GENMASK(25, 16)
287 #define BIT_MASK_RES_RX GENMASK(25, 16)
[all …]
/freebsd-14.2/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h225 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
226 #define MT_IFS_RIFS GENMASK(14, 10)
227 #define MT_IFS_SIFS GENMASK(22, 16)
228 #define MT_IFS_SLOT GENMASK(30, 24)
231 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
262 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
277 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
469 #define MT_WTBL_LMAC_DW GENMASK(7, 2)
853 #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
893 #define MT_ADIE_IDX0 GENMASK(15, 0)
[all …]
H A Dmac.h9 #define MT_TX_FREE_VER GENMASK(18, 16)
10 #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)
12 #define MT_TX_FREE_COUNT GENMASK(12, 0)
13 #define MT_TX_FREE_COUNT_V3 GENMASK(27, 24)
14 #define MT_TX_FREE_STAT GENMASK(14, 13)
15 #define MT_TX_FREE_STAT_V3 GENMASK(29, 28)
29 #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
30 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
34 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
36 #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
[all …]

1234567