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Searched refs:GCNSubtarget (Results 1 – 25 of 98) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSubtarget.cpp40 #define AMDGPUSubtarget GCNSubtarget
62 GCNSubtarget::~GCNSubtarget() = default;
64 GCNSubtarget &
174 GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, in GCNSubtarget() function in GCNSubtarget
645 bool GCNSubtarget::hasMadF16() const { in hasMadF16()
649 bool GCNSubtarget::useVGPRIndexMode() const { in useVGPRIndexMode()
653 bool GCNSubtarget::useAA() const { return UseAA; } in useAA()
728 unsigned GCNSubtarget::getBaseMaxNumSGPRs( in getBaseMaxNumSGPRs()
812 unsigned GCNSubtarget::getBaseMaxNumVGPRs( in getBaseMaxNumVGPRs()
951 const GCNSubtarget &ST = DAGInstrs->MF.getSubtarget<GCNSubtarget>(); in apply()
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H A DAMDGPUResourceUsageAnalysis.h23 class GCNSubtarget; variable
45 int32_t getTotalNumSGPRs(const GCNSubtarget &ST) const;
48 int32_t getTotalNumVGPRs(const GCNSubtarget &ST, int32_t NumAGPR,
50 int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
H A DSIFrameLowering.cpp79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister()
385 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionFlatScratchInit()
541 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getEntryFunctionReservedScratchRsrcReg()
610 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionPrologue()
728 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEntryFunctionScratchRsrcRegSetup()
889 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in buildScratchExecCopy()
920 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitCSRSpillStores()
1006 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitCSRSpillRestores()
1078 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitPrologue()
1227 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitEpilogue()
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H A DAMDGPUAsmPrinter.cpp156 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyStart()
225 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyEnd()
263 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionEntryLabel()
423 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getAmdhsaKernelDescriptor()
473 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
663 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getFunctionCodeSize()
687 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getSIProgramInfo()
973 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in EmitProgramInfoSI()
1040 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in EmitPALMetadata()
1125 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in emitPALFunctionMetadata()
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H A DAMDGPUPreLegalizerCombiner.cpp47 const GCNSubtarget &STI;
56 const GCNSubtarget &STI, MachineDominatorTree *MDT,
79 #define AMDGPUSubtarget GCNSubtarget
86 #define AMDGPUSubtarget GCNSubtarget
95 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPreLegalizerCombinerImpl()
277 const GCNSubtarget &STI = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DSIProgramInfo.h24 class GCNSubtarget; variable
91 uint64_t getComputePGMRSrc1(const GCNSubtarget &ST) const;
92 uint64_t getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST) const;
H A DSIMachineFunctionInfo.cpp33 const GCNTargetMachine &getTM(const GCNSubtarget *STI) { in getTM()
39 const GCNSubtarget *STI) in SIMachineFunctionInfo()
46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI); in SIMachineFunctionInfo()
183 const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>(); in limitOccupancy()
317 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in shiftSpillPhysVGPRsToLowestRange()
360 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocatePhysicalVGPRForSGPRSpills()
404 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateSGPRSpillToVGPRLane()
445 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in allocateVGPRSpillToAGPR()
587 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getGITPtrLoReg()
H A DAMDGPUAttributor.cpp155 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in hasApertureRegs()
161 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in supportsGetDoorbellID()
166 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getFlatWorkGroupSizes()
172 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaximumFlatWorkGroupRange()
187 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getWavesPerEU()
195 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getEffectiveWavesPerEU()
200 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in getMaxWavesPerEU()
922 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F); in addPreloadKernArgHint()
H A DSILowerSGPRSpills.cpp93 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRSaves()
136 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in insertCSRRestores()
213 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in spillCalleeSavedRegs()
309 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPUGlobalISelUtils.h18 class GCNSubtarget; variable
30 bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty);
H A DGCNVOPDUtils.cpp43 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>(); in checkVOPDRegConstraints()
159 const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>(); in apply()
H A DAMDGPURegBankCombiner.cpp48 const GCNSubtarget &STI;
60 const GCNSubtarget &STI, MachineDominatorTree *MDT,
101 #define AMDGPUSubtarget GCNSubtarget
108 #define AMDGPUSubtarget GCNSubtarget
117 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPURegBankCombinerImpl()
449 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPURemoveIncompatibleFunctions.cpp83 const SubtargetSubTypeKV *getGPUInfo(const GCNSubtarget &ST, in getGPUInfo()
139 const GCNSubtarget *ST = in checkFunction()
140 static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F)); in checkFunction()
H A DGCNIterativeScheduler.cpp92 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printRegions()
115 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in printSchedRP()
297 &MF.getSubtarget<GCNSubtarget>()); in schedule()
398 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleRegion()
412 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in sortRegionsByPressure()
429 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in tryMaximizeOccupancy()
466 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleLegacyMaxOccupancy()
520 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleMinReg()
554 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in scheduleILP()
H A DSIFixVGPRCopies.cpp53 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPUTargetMachine.cpp458 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createGCNMaxOccupancyMachineScheduler()
480 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeGCNMaxOccupancyMachineScheduler()
496 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createIterativeILPMachineScheduler()
886 I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this); in getSubtargetImpl()
932 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createPostMachineScheduler()
1145 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1166 const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>(); in createMachineScheduler()
1495 Allocator, F, static_cast<const GCNSubtarget *>(STI)); in createMachineFunctionInfo()
1506 *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF); in convertFuncInfoToYAML()
1516 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in parseMachineFunctionInfo()
H A DAMDGPURegBankSelect.cpp63 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in INITIALIZE_PASS_DEPENDENCY()
H A DAMDGPUInstrInfo.h22 class GCNSubtarget; variable
28 explicit AMDGPUInstrInfo(const GCNSubtarget &st);
H A DGCNRegPressure.h63 unsigned getOccupancy(const GCNSubtarget &ST) const { in getOccupancy()
73 bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const { in higherOccupancy()
77 bool less(const GCNSubtarget &ST, const GCNRegPressure& O,
110 friend Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST);
329 Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST = nullptr);
H A DAMDGPUInstructionSelector.h22 #define AMDGPUSubtarget GCNSubtarget
38 class GCNSubtarget; variable
51 const GCNSubtarget *Subtarget;
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
369 const GCNSubtarget &STI;
372 #define AMDGPUSubtarget GCNSubtarget
H A DAMDGPUPostLegalizerCombiner.cpp48 const GCNSubtarget &STI;
58 const GCNSubtarget &STI, MachineDominatorTree *MDT,
117 #define AMDGPUSubtarget GCNSubtarget
124 #define AMDGPUSubtarget GCNSubtarget
133 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) in AMDGPUPostLegalizerCombinerImpl()
517 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPUCallLowering.cpp212 const GCNSubtarget &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>(); in getStackAddress()
245 const auto &ST = MF.getSubtarget<GCNSubtarget>(); in assignValueToAddress()
514 const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>(); in lowerFormalArgumentsKernel()
599 const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>(); in lowerFormalArguments()
795 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in passSpecialInputs()
1007 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in doCallerAndCalleePassArgsTheSameWay()
1072 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in areCalleeOutgoingArgsTailCallable()
1112 const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo(); in isEligibleForTailCallOptimization()
1157 const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo, in handleImplicitCallArguments()
1184 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in lowerTailCall()
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H A DSILateBranchLowering.cpp85 const GCNSubtarget &ST = MBB.getParent()->getSubtarget<GCNSubtarget>(); in generateEndPgm()
149 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.h27 class GCNSubtarget; variable
44 const GCNSubtarget &Subtarget;
166 AMDGPURegisterBankInfo(const GCNSubtarget &STI);
H A DGCNSchedStrategy.h24 class GCNSubtarget; variable
174 const GCNSubtarget &ST;
255 const GCNSubtarget &ST;
388 bool sinkTriviallyRematInsts(const GCNSubtarget &ST,

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