Home
last modified time | relevance | path

Searched refs:GATE (Results 1 – 18 of 18) sorted by relevance

/freebsd-14.2/sys/arm64/rockchip/clk/
H A Drk3399_cru.c81 GATE(0, "npll_cs", "npll", 2, 10),
82 GATE(0, "gpll_cs", "gpll", 2, 9),
83 GATE(0, "cpll_cs", "cpll", 2, 8),
85 GATE(0, "gpll_cci_trace", "gpll", 2, 6),
86 GATE(0, "cpll_cci_trace", "cpll", 2, 5),
88 GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3),
89 GATE(0, "npll_aclk_cci_src", "npll", 2, 2),
90 GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1),
91 GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0),
99 GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3),
[all …]
H A Drk3568_cru.c818 GATE(0, "atclk_core", "atclk_core_div", 0, 8),
819 GATE(0, "gicclk_core", "gicclk_core_div", 0, 9),
850 GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c", 2, 3),
913 GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15),
979 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9),
1119 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0),
1120 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1),
1121 GATE(CLK_ISP, "clk_isp", "clk_isp_c", 19, 2),
1141 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9),
1289 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1),
[all …]
H A Drk3288_cru.c91 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
92 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
93 GATE(0, "gpll_ddr", "gpll", 0, 9),
94 GATE(0, "dpll_ddr", "dpll", 0, 8),
99 GATE(0, "gpll_core", "gpll", 0, 2),
100 GATE(0, "apll_core", "apll", 0, 1),
142 GATE(0, "vip_src", "vip_src_s", 3, 7),
153 GATE(0, "jtag", "ext_jtag", 4, 14),
166 GATE(0, "i2s_src", "i2s_src_s", 4, 1),
281 GATE(0, "l2ram", "l2ram_s", 12, 4),
[all …]
H A Drk3328_cru.c254 GATE(0, "core_apll_clk", "apll", 0, 0),
255 GATE(0, "core_dpll_clk", "dpll", 0, 1),
256 GATE(0, "core_gpll_clk", "gpll", 0, 2),
265 GATE(0, "core_npll_clk", "npll", 0, 12),
316 GATE(0, "periph_gclk_src", "gpll", 4, 0),
317 GATE(0, "periph_cclk_src", "cpll", 4, 1),
452 GATE(0, "pclk_cru", "pclk_bus", 17, 4),
454 GATE(0, "pclk_sgrf", "pclk_bus", 17, 6),
458 GATE(0, "pclk_sim", "pclk_bus", 17, 10),
562 GATE(0, "pclk_pmu", "pclk_bus", 28, 3),
[all …]
H A Drk3568_pmucru.c165 GATE(PCLK_PDPMU, "pclk_pdpmu", "pclk_pdpmu_pre", 0, 2),
166 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6),
167 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
170 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0),
171 GATE(CLK_I2C0, "clk_i2c0", "clk_i2c0_div", 1, 1),
172 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),
176 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 1, 6),
177 GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_div", 1, 7),
179 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 1, 9),
182 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12),
[all …]
H A Drk3399_pmucru.c95 GATE(SCLK_SPI3_PMU, "clk_spi3_pmu", "clk_spi3_c", 0, 2),
99 GATE(0, "clk_uart4_frac", "clk_uart4_frac_frac", 0, 6),
101 GATE(SCLK_WIFI_PMU, "clk_wifi_pmu", "clk_wifi_sel", 0, 8),
102 GATE(SCLK_I2C0_PMU, "clk_i2c0_src", "clk_i2c0_div", 0, 9),
103 GATE(SCLK_I2C4_PMU, "clk_i2c4_src", "clk_i2c4_div", 0, 10),
104 GATE(SCLK_I2C8_PMU, "clk_i2c8_src", "clk_i2c8_div", 0, 11),
108 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 1, 0),
115 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 1, 7),
116 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 1, 8),
117 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 1, 9),
[all …]
H A Drk_cru.h50 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
/freebsd-14.2/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c310 GATE(ISPB, "ispb", "clk_m", L(3)),
311 GATE(RTC, "rtc", "clk_s", L(4)),
325 GATE(VI, "vi", "pc_vi", L(20)),
334 GATE(MC, "mem", "clk_m", H(0)),
338 GATE(PMC, "pmc", "clk_s", H(6)),
360 GATE(AFI, "afi", "clk_m", U(8)),
363 GATE(DTV, "dtv", "clk_m", U(15)),
408 GATE(CEC, "cec", "clk_m", W(8)),
424 GATE(MC1, "mc1", "clk_m", W(30)),
430 GATE(ETR, "etr", "clk_m", X(3)),
[all …]
H A Dtegra210_car.c123 #define GATE(_id, cname, plist, o, s) \ macro
248 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
249 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
250 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21),
251 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29),
252 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
H A Dtegra210_clk_pll.c209 #define GATE(_id, cname, plist, o, s) \ macro
511 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
512 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
513 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
/freebsd-14.2/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c216 GATE(ISPB, "ispb", "clk_m", L(3)),
217 GATE(RTC, "rtc", "clk_s", L(4)),
230 GATE(PWM, "pwm", "pc_pwm", L(17)),
232 GATE(VI, "vi", "pc_vi", L(20)),
234 GATE(ISP, "isp", "pc_isp", L(23)),
238 GATE(VCP, "vcp", "clk_m", L(29)),
243 GATE(MC, "mem", "clk_m", H(0)),
246 GATE(KBC, "kbc", "clk_s", H(4)),
277 GATE(OWR, "owr", "pc_owr", U(7)),
278 GATE(AFI, "afi", "clk_m", U(8)),
[all …]
H A Dtegra124_car.c122 #define GATE(_id, cname, plist, o, s) \ macro
257 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
258 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
/freebsd-14.2/sys/arm64/freescale/imx/
H A Dimx8mq_ccm.c168 GATE(IMX8MQ_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x28, 21),
169 GATE(IMX8MQ_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x18, 21),
170 GATE(IMX8MQ_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x20, 21),
171 GATE(IMX8MQ_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x0, 21),
172 GATE(IMX8MQ_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x8, 21),
175 GATE(IMX8MQ_SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, 9),
176 GATE(IMX8MQ_SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, 11),
177 GATE(IMX8MQ_SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, 13),
178 GATE(IMX8MQ_SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, 15),
179 GATE(IMX8MQ_SYS1_PLL_160M_CG, "sys1_pll_160m_cg", "sys1_pll_out", 0x30, 17),
[all …]
H A Dimx_ccm_clk.h121 #define GATE(_id, _name, _pname, _o, _shift) \ macro
/freebsd-14.2/sys/riscv/sifive/
H A Dsifive_prci.c147 #define GATE(_id, _name, _parent_name, _base) \ macro
155 #define GATE_END GATE(0, NULL, NULL, 0)
242 GATE(FU740_PRCI_PCIEAUXCLK, "pcieauxclk", "hfclk", FU740_PRCI_PCIEAUX_GATE),
/freebsd-14.2/crypto/heimdal/lib/wind/
H A DUnicodeData.txt8129 2ED4;CJK RADICAL C-SIMPLIFIED GATE;So;0;ON;;;;;N;;;;;
8329 2FA8;KANGXI RADICAL GATE;So;0;ON;<compat> 9580;;;;N;;;;;
H A DNormalizationTest.txt1604 2FA8;2FA8;2FA8;9580;9580; # (⾨; ⾨; ⾨; 門; 門; ) KANGXI RADICAL GATE
/freebsd-14.2/share/misc/
H A Dusb_vendors6948 018b Hi-MD SOUND GATE