Searched refs:FinalReg (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandPseudoInsts.cpp | 567 Register FinalReg = MI.getOperand(0).getReg(); in expandLoadTLSDescAddress() local
594 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg) in expandLoadTLSDescAddress()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1686 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1707 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()
1708 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
1710 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
1720 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 963 FinalReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
1019 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg) in emitStackProbeInlineWindowsCoreCLR64()
1037 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInlineWindowsCoreCLR64()
1044 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInlineWindowsCoreCLR64()
1046 .addReg(FinalReg) in emitStackProbeInlineWindowsCoreCLR64()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1602 unsigned FinalReg = SubReg; in buildSpillLoadStore() local
1675 FinalReg) in buildSpillLoadStore()
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