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Searched refs:FSUB (Results 1 – 25 of 61) sorted by relevance

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/freebsd-14.2/bin/pax/
H A Doptions.c99 FSUB fsub[] = {
193 FSUB tmp; in pax_options()
370 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in pax_options()
371 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) { in pax_options()
377 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in pax_options()
1026 FSUB tmp; in cpio_options()
1192 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, in cpio_options()
1193 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) in cpio_options()
1197 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) in cpio_options()
1305 return(strcmp(((const FSUB *)a)->name, ((const FSUB *)b)->name)); in c_frmt()
H A Dextern.h182 extern FSUB fsub[];
205 extern FSUB *frmt;
H A Dpax.h73 typedef struct fsub FSUB; typedef
H A Dpax.c73 FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c567 FSUB *orgfrmt; in append()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td83 FSUB,
H A DP9InstrResources.td419 (instregex "FSUB(S)?$"),
477 (instregex "FSUB(S)?_rec$"),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def113 ADD_BINARY_VVP_OP_COMPACT(FSUB) REGISTER_PACKED(VVP_FSUB)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1054 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd in getArithmeticInstrCost()
1118 { ISD::FSUB, MVT::f64, { 1, 4, 1, 1 } }, // vsubsd in getArithmeticInstrCost()
1119 { ISD::FSUB, MVT::f32, { 1, 4, 1, 1 } }, // vsubss in getArithmeticInstrCost()
1120 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd in getArithmeticInstrCost()
1121 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps in getArithmeticInstrCost()
1122 { ISD::FSUB, MVT::v4f64, { 1, 4, 1, 2 } }, // vsubpd in getArithmeticInstrCost()
1123 { ISD::FSUB, MVT::v8f32, { 1, 4, 1, 2 } }, // vsubps in getArithmeticInstrCost()
1252 { ISD::FSUB, MVT::f64, { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
1253 { ISD::FSUB, MVT::f32 , { 1, 3, 1, 1 } }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
1417 { ISD::FSUB, MVT::f64, { 2, 3, 1, 1 } }, // (x87) in getArithmeticInstrCost()
[all …]
H A DX86IntrinsicsInfo.h930 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
931 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
1209 X86_INTRINSIC_DATA(avx512fp16_sub_ph_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def53 DAG_INSTRUCTION(FSub, 2, 1, experimental_constrained_fsub, FSUB)
H A DVPIntrinsics.def318 HELPER_REGISTER_BINARY_FP_VP(fsub, VP_FSUB, FSub, FSUB)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h391 FSUB, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp352 case ISD::FSUB: in LegalizeOp()
949 case ISD::FSUB: in Expand()
1676 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { in ExpandFNEG()
1680 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero, in ExpandFNEG()
H A DSelectionDAGBuilder.cpp5162 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); in getLimitedPrecisionExp2()
5300 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5317 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5342 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog()
5348 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog()
5413 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5439 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, in expandLog2()
5445 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, in expandLog2()
5508 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
5529 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, in expandLog10()
[all …]
H A DSelectionDAGBuilder.h542 void visitFSub(const User &I) { visitBinary(I, ISD::FSUB); } in visitFSub()
H A DSelectionDAGDumper.cpp267 case ISD::FSUB: return "fsub"; in getOperationName()
H A DLegalizeFloatTypes.cpp134 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; in SoftenFloatResult()
1355 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; in ExpandFloatResult()
2432 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; in PromoteFloatResult()
2841 case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break; in SoftPromoteHalfResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp592 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
608 case ISD::FSUB: in getArithmeticInstrCost()
H A DAMDGPUISelLowering.cpp381 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
486 ISD::FSQRT, ISD::FSIN, ISD::FSUB, in AMDGPUTargetLowering()
575 ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
602 case ISD::FSUB: in fnegFoldsIntoOpcode()
2423 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
2466 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2640 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2717 SDValue YT = DAG.getNode(ISD::FSUB, DL, VT, Y, YH, Flags); in LowerFLOGCommon()
2740 R = DAG.getNode(ISD::FSUB, DL, VT, R, Shift, Flags); in LowerFLOGCommon()
3023 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
H A DAArch64SchedA57.td446 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
H A DAArch64SchedKryoDetails.td639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td40 defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td124 defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;

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