Home
last modified time | relevance | path

Searched refs:FSHR (Results 1 – 23 of 23) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h711 FSHR, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp240 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
316 setOperationAction(ISD::FSHR, T, Custom); in initializeHVXLowering()
2075 assert(Opc == ISD::FSHL || Opc == ISD::FSHR); in LowerHvxFunnelShift()
3180 case ISD::FSHR: in LowerHvxOperation()
3220 case ISD::FSHR: return LowerHvxFunnelShift(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1576 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1577 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp264 case ISD::FSHR: return "fshr"; in getOperationName()
H A DLegalizeIntegerTypes.cpp290 case ISD::FSHR: in PromoteIntegerResult()
1397 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
1833 case ISD::FSHR: Res = PromoteIntOp_FunnelShift(N); break; in PromoteIntegerOperand()
2769 case ISD::FSHR: in ExpandIntegerResult()
4179 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
4181 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
5021 unsigned Opcode = N->getOpcode() == ISD::ROTL ? ISD::FSHL : ISD::FSHR; in ExpandIntRes_Rotate()
H A DLegalizeVectorOps.cpp363 case ISD::FSHR: in LegalizeOp()
1020 case ISD::FSHR: in Expand()
H A DTargetLowering.cpp2101 case ISD::FSHR: { in SimplifyDemandedBits()
4346 (N0.getOpcode() != ISD::FSHL && N0.getOpcode() != ISD::FSHR)) in foldSetCCWithFunnelShift()
4356 if (N0.getOpcode() == ISD::FSHR) in foldSetCCWithFunnelShift()
7857 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
8008 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
10239 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
H A DDAGCombiner.cpp1977 case ISD::FSHR: return visitFunnelShift(N); in visit()
5850 if ((HandOpcode == ISD::FSHL || HandOpcode == ISD::FSHR) && in hoistLogicOpWithSameOpcodeHands()
7825 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL && in visitORCommutative()
8372 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8373 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
8382 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
8383 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
8403 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
8570 Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
8618 LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
[all …]
H A DLegalizeVectorTypes.cpp169 case ISD::FSHR: in ScalarizeVectorResult()
1180 case ISD::FSHR: in SplitVectorResult()
4327 case ISD::FSHR: in WidenVectorResult()
H A DLegalizeDAG.cpp1284 case ISD::FSHR: in LegalizeOp()
3806 case ISD::FSHR: in ExpandNode()
H A DSelectionDAG.cpp3469 case ISD::FSHR: in computeKnownBits()
5023 case ISD::FSHR: in canCreateUndefOrPoison()
H A DSelectionDAGBuilder.cpp6828 auto FunnelOpcode = IsFSHL ? ISD::FSHL : ISD::FSHR; in visitIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def294 VP_PROPERTY_FUNCTIONAL_SDOPC(FSHR)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h40 FSHR, enumerator
H A DX86InstrFragments.td133 def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>;
H A DX86ISelLowering.cpp207 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
1233 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1439 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1896 setOperationAction(ISD::FSHR, MVT::v64i8, Custom); in X86TargetLowering()
1898 setOperationAction(ISD::FSHR, MVT::v32i16, Custom); in X86TargetLowering()
1900 setOperationAction(ISD::FSHR, MVT::v16i32, Custom); in X86TargetLowering()
1970 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
1982 setOperationAction(ISD::FSHR, VT, Custom); in X86TargetLowering()
29659 bool IsFSHR = Op.getOpcode() == ISD::FSHR; in LowerFunnelShift()
29864 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp837 ISD::FSHL, ISD::FSHR, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td413 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp904 ISD::FSHR, in SITargetLowering()
11660 case ISD::FSHR: { in calculateByteProvider()
11966 if (N->getOpcode() == ISD::FSHR && in matchPERM()
14399 case ISD::FSHR: { in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp428 setOperationAction(ISD::FSHR, MVT::i32, Legal); in AMDGPUTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp753 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
756 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
11657 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
11784 case ISD::FSHR: in ReplaceNodeResults()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp521 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FSHL, ISD::FSHR, in NVPTXTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp567 setOperationAction(ISD::FSHR, MVT::i32, Custom); in AArch64TargetLowering()
568 setOperationAction(ISD::FSHR, MVT::i64, Custom); in AArch64TargetLowering()
6054 ISD::FSHR, DL, VT, Op.getOperand(0), Op.getOperand(1), in LowerFunnelShift()
6056 } else if (Op.getOpcode() == ISD::FSHR) { in LowerFunnelShift()
6425 case ISD::FSHR: in LowerOperation()