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Searched refs:FRM (Results 1 – 11 of 11) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZvfbf.td24 let Uses = [FRM] in
30 RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in {
H A DRISCVInsertReadWriteCSR.cpp81 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
H A DRISCVInstrInfoV.td1343 let Uses = [FRM], mayRaiseFPException = true in {
1351 Uses = [FRM],
1368 let Uses = [FRM], mayRaiseFPException = true in {
1376 Uses = [FRM], mayRaiseFPException = true in {
1381 let Uses = [FRM], mayRaiseFPException = true in {
1393 let Uses = [FRM], mayRaiseFPException = true in {
1467 let Uses = [FRM] in {
1473 let Uses = [FRM] in {
1482 let Uses = [FRM] in {
1495 let Uses = [FRM] in {
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H A DRISCVInstrInfo.cpp1635 const MachineOperand &FRM = Root.getOperand(FrmOpIdx); in finalizeInsInstrs() local
1644 MIB.add(FRM); in finalizeInsInstrs()
1645 if (FRM.getImm() == RISCVFPRndMode::DYN) in finalizeInsInstrs()
1646 MIB.addUse(RISCV::FRM, RegState::Implicit); in finalizeInsInstrs()
H A DRISCVRegisterInfo.cpp130 markSuperRegs(Reserved, RISCV::FRM); in getReservedRegs()
H A DRISCVISelLowering.cpp2938 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3041 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3100 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
13864 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INTCombine()
13897 if (FRM == RISCVFPRndMode::RTZ) { in performFP_TO_INTCombine()
13903 } else if (FRM == RISCVFPRndMode::DYN) { in performFP_TO_INTCombine()
13974 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INT_SATCombine()
17003 .add(MachineOperand::CreateReg(RISCV::FRM, in emitVFROUND_NOEXCEPT_MASK()
17017 .add(MachineOperand::CreateReg(RISCV::FRM, in emitVFROUND_NOEXCEPT_MASK()
17112 int64_t FRM = MI.getOperand(3).getImm(); in emitFROUND() local
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H A DRISCVInstrInfo.td1887 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
1888 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
1889 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
1890 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
H A DRISCVRegisterInfo.td606 def FRM : RISCVReg<0, "frm">;
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dste-href-family-pinctrl.dtsi19 pins = "GPIO216_AG12"; /* FRM */
57 "GPIO216_AG12", /* FRM */
H A Dste-snowball.dts565 pins = "GPIO144_B13"; /* FRM */
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp332 FRM, enumerator
366 RISCVFPRndMode::RoundingMode FRM; member
394 struct FRMOp FRM; member
427 case KindTy::FRM: in RISCVOperand()
428 FRM = o.FRM; in RISCVOperand()
597 bool isFRMArg() const { return Kind == KindTy::FRM; } in isFRMArg()
599 bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; } in isRTZArg()
1011 return FRM.FRM; in getFRM()
1047 case KindTy::FRM: in print()
1124 Op->FRM.FRM = FRM; in createFRMArg()
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