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Searched refs:FRINT (Results 1 – 25 of 48) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def93 DAG_FUNCTION(rint, 1, 1, experimental_constrained_rint, FRINT)
H A DVPIntrinsics.def431 VP_PROPERTY_FUNCTIONAL_SDOPC(FRINT)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h952 FRINT, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td822 def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",
823 "^FRINT(32|64)[XZ][SD]r$")>;
1121 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
1122 "^FRINT[32|64)[XZ]v2f(32|64)$")>;
1126 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
1127 "^FRINT(32|64)[XZ]v4f32$")>;
1131 def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
2034 def : InstRW<[N2Write_6cyc_4V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H$")>;
2037 def : InstRW<[N2Write_4cyc_2V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S$")>;
2040 def : InstRW<[N2Write_3cyc_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D$")>;
H A DAArch64SchedNeoverseN1.td438 def : InstRW<[N1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ][HSD]r$",
439 "^FRINT(32|64)[XZ][SD]r$")>;
735 def : InstRW<[N1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>;
738 def : InstRW<[N1Write_4c_2V0], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>;
741 def : InstRW<[N1Write_6c_4V0], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
H A DAArch64SchedNeoverseV1.td689 def : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",
690 "^FRINT(32|64)[XZ][SD]r$")>;
963 def : InstRW<[V1Write_3c_1V02], (instregex "^FRINT[AIMNPXZ]v2f(32|64)$")>;
966 def : InstRW<[V1Write_4c_2V02], (instregex "^FRINT[AIMNPXZ]v4f(16|32)$")>;
969 def : InstRW<[V1Write_6c_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
1639 def : InstRW<[V1Write_6c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H$")>;
1642 def : InstRW<[V1Write_4c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S$")>;
1645 def : InstRW<[V1Write_3c_1V0], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D$")>;
H A DAArch64SchedNeoverseV2.td1313 def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ][HSD]r$",
1314 "^FRINT(32|64)[XZ][SD]r$")>;
1621 (instregex "^FRINT[AIMNPXZ]v2f(32|64)$",
1622 "^FRINT(32|64)[XZ]v2f(32|64)$")>;
1626 (instregex "^FRINT[AIMNPXZ]v4f(16|32)$",
1627 "^FRINT(32|64)[XZ]v4f32$")>;
1630 def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]v8f16$")>;
2561 def : InstRW<[V2Write_6cyc_4V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
2564 def : InstRW<[V2Write_4cyc_2V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
2567 def : InstRW<[V2Write_3cyc_1V02], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
H A DAArch64SchedA57.td512 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
514 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
586 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
H A DAArch64SchedAmpere1.td888 def : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if]16")>;
917 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if](32|64)")>;
918 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FRINT(32|64)")>;
H A DAArch64SchedAmpere1B.td860 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if]16")>;
899 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT[AIMNPXZ]v.[if](32|64)")>;
900 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FRINT(32|64)")>;
H A DAArch64SchedFalkorDetails.td592 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)v2f32$")>;
617 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)$")>;
1123 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FRINT(A|I|M|N|P|X|Z)(S|D)r$")>;
H A DAArch64SchedExynosM3.td546 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
661 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedTSV110.td508 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT.+r")>;
698 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedA64FX.td1315 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1560 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1563 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
2088 "^FRINT._Z", "^FSCALE_Z", "^FTMAD_Z", "^FTSMUL_Z",
H A DAArch64SchedA510.td1118 def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_H")>;
1121 def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_S")>;
1124 def : InstRW<[CortexA510Write<4, CortexA510UnitVALU>], (instregex "^FRINT[AIMNPXZ]_ZPmZ_D")>;
H A DAArch64SchedExynosM4.td657 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT.+r")>;
802 def : InstRW<[M4WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedExynosM5.td716 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT.+r")>;
840 def : InstRW<[M5WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
H A DAArch64SchedThunderX2T99.td1188 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1414 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1417 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedThunderX3T110.td1296 (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)")>;
1522 (instregex "^FRINT[AIMNPXZ](v2f32)")>;
1525 (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
H A DAArch64SchedKryoDetails.td963 (instregex "FRINT(A|I|M|N|P|X|Z)(S|D)r")>;
969 (instregex "FRINT(A|I|M|N|P|X|Z)v2f32")>;
975 (instregex "FRINT(A|I|M|N|P|X|Z)(v2f64|v4f32)")>;
H A DAArch64SchedCyclone.td580 // FRINT(AIMNPXZ) V,V
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp215 case ISD::FRINT: return "frint"; in getOperationName()
H A DLegalizeFloatTypes.cpp124 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
1345 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
2414 case ISD::FRINT: in PromoteFloatResult()
2823 case ISD::FRINT: in SoftPromoteHalfResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp144 setOperationAction(ISD::FRINT, MVT::f16, Promote); in MipsSETargetLowering()
386 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
1905 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp356 setOperationAction(ISD::FRINT, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
485 ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
615 case ISD::FRINT: in fnegFoldsIntoOpcode()
1343 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
4833 case ISD::FRINT: in performFNegCombine()

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