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Searched refs:FP_TO_SINT_SAT (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h855 FP_TO_SINT_SAT, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp155 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
180 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
266 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
1482 case ISD::FP_TO_SINT_SAT: in LowerOperation()
2563 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2603 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2648 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2880 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp373 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat"; in getOperationName()
H A DLegalizeVectorOps.cpp440 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
1078 case ISD::FP_TO_SINT_SAT: in Expand()
H A DLegalizeFloatTypes.cpp927 case ISD::FP_TO_SINT_SAT: in SoftenFloatOperand()
2236 case ISD::FP_TO_SINT_SAT: in PromoteFloatOperand()
3137 case ISD::FP_TO_SINT_SAT: in SoftPromoteHalfOperand()
H A DLegalizeVectorTypes.cpp180 case ISD::FP_TO_SINT_SAT: in ScalarizeVectorResult()
1192 case ISD::FP_TO_SINT_SAT: in SplitVectorResult()
3022 case ISD::FP_TO_SINT_SAT: in SplitVectorOperand()
4259 case ISD::FP_TO_SINT_SAT: in WidenVectorResult()
6084 case ISD::FP_TO_SINT_SAT: in WidenVectorOperand()
H A DLegalizeDAG.cpp1170 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
3368 case ISD::FP_TO_SINT_SAT: in ExpandNode()
5009 case ISD::FP_TO_SINT_SAT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp160 case ISD::FP_TO_SINT_SAT: in PromoteIntegerResult()
2639 case ISD::FP_TO_SINT_SAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp4409 case ISD::FP_TO_SINT_SAT: in ComputeNumSignBits()
6809 case ISD::FP_TO_SINT_SAT: in getNode()
H A DSelectionDAGBuilder.cpp6650 setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, in visitIntrinsicCall()
H A DTargetLowering.cpp10705 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in expandFP_TO_INT_SAT()
H A DDAGCombiner.cpp5633 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp845 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp591 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering()
756 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
814 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1138 setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, in RISCVTargetLowering()
1398 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering()
2743 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in lowerFP_TO_INT_SAT()
6290 case ISD::FP_TO_SINT_SAT: in LowerOperation()
13977 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT_SAT; in performFP_TO_INT_SATCombine()
15514 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp553 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in AArch64TargetLowering()
554 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in AArch64TargetLowering()
990 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
1098 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1729 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in addTypeForNEON()
4177 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerVectorFP_TO_INT_SAT()
4233 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerFP_TO_INT_SAT()
6263 case ISD::FP_TO_SINT_SAT: in LowerOperation()
17375 if (N->getOpcode() == ISD::FP_TO_SINT_SAT || in performFpToIntCombine()
17384 N->getOpcode() == ISD::FP_TO_SINT_SAT); in performFpToIntCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td540 def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp310 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in addMVEVectorTypes()
777 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in ARMTargetLowering()
779 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in ARMTargetLowering()
5944 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
10573 case ISD::FP_TO_SINT_SAT: in LowerOperation()
10766 case ISD::FP_TO_SINT_SAT: in ReplaceNodeResults()
H A DARMISelDAGToDAG.cpp3786 case ISD::FP_TO_SINT_SAT: in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp293 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
297 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in X86TargetLowering()
21095 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
31901 case ISD::FP_TO_SINT_SAT: in LowerOperation()