| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 914 FP_TO_FP16, enumerator
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.h | 526 FP_TO_FP16, enumerator
|
| H A D | AMDGPUInstrInfo.td | 144 def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
|
| H A D | AMDGPUISelLowering.cpp | 407 setOperationAction(ISD::FP_TO_FP16, {MVT::f64, MVT::f32}, Custom); in AMDGPUTargetLowering()
1361 case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); in LowerOperation()
3476 return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0); in LowerFP_TO_FP16()
5452 NODE_NAME_CASE(FP_TO_FP16) in getTargetNodeName()
5602 case AMDGPUISD::FP_TO_FP16: { in computeKnownBitsForTargetNode()
5771 case AMDGPUISD::FP_TO_FP16: in ComputeNumSignBitsForTargetNode()
|
| H A D | SIISelLowering.cpp | 572 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote); in SITargetLowering()
573 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32); in SITargetLowering()
6275 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src); in lowerFP_ROUND()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 919 case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes in SoftenFloatOperand()
970 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
980 if (N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
2179 return ISD::FP_TO_FP16; in GetPromotionOpcode()
2386 case ISD::FP_TO_FP16: in PromoteFloatResult()
|
| H A D | SelectionDAGDumper.cpp | 379 case ISD::FP_TO_FP16: return "fp_to_fp16"; in getOperationName()
|
| H A D | LegalizeDAG.cpp | 1023 case ISD::FP_TO_FP16: in LegalizeOp()
3644 case ISD::FP_TO_FP16: in ExpandNode()
3650 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) { in ExpandNode()
3657 DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal)); in ExpandNode()
4646 case ISD::FP_TO_FP16: { in ConvertNodeToLibcall()
|
| H A D | LegalizeIntegerTypes.cpp | 165 case ISD::FP_TO_FP16: in PromoteIntegerResult()
437 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp)); in PromoteIntRes_BITCAST()
|
| H A D | SelectionDAG.cpp | 5600 case ISD::FP_TO_FP16: in getNode()
6203 case ISD::FP_TO_FP16: in FoldConstantArithmetic()
6208 (void)V.convert(Opcode == ISD::FP_TO_FP16 ? APFloat::IEEEhalf() in FoldConstantArithmetic()
|
| H A D | DAGCombiner.cpp | 2052 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N); in visit()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1702 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in SparcTargetLowering()
1704 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in SparcTargetLowering()
1706 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); in SparcTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 121 ISD::FREM, ISD::FCOPYSIGN, ISD::FP16_TO_FP, ISD::FP_TO_FP16}; in CSKYTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1789 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in HexagonTargetLowering()
1790 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in HexagonTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 446 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in MipsTargetLowering()
448 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in MipsTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 137 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 221 setOperationAction(ISD::FP_TO_FP16, FPVT, Expand); in initSPUActions()
|
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 543 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 535 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); in RISCVTargetLowering()
579 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Custom); in RISCVTargetLowering()
6322 case ISD::FP_TO_FP16: { in LowerOperation()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 212 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in PPCTargetLowering()
215 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in PPCTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1483 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in ARMTargetLowering()
1489 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in ARMTargetLowering()
|
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 395 for (auto Op : {ISD::FP16_TO_FP, ISD::STRICT_FP16_TO_FP, ISD::FP_TO_FP16, in X86TargetLowering()
31909 case ISD::FP_TO_FP16: in LowerOperation()
55910 if (N->getOperand(0).getOpcode() != ISD::FP_TO_FP16) in combineFP16_TO_FP()
|