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Searched refs:FP_ROUND (Results 1 – 25 of 36) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def62 DAG_INSTRUCTION(FPTrunc, 1, 1, experimental_constrained_fptrunc, FP_ROUND)
H A DVPIntrinsics.def470 HELPER_REGISTER_FP_CAST_VP(fptrunc, VP_FP_ROUND, FPTrunc, FP_ROUND, 1)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h869 FP_ROUND, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp109 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; in SoftenFloatResult()
922 case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; in SoftenFloatOperand()
970 assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || in SoftenFloatOp_FP_ROUND()
1158 DAG.getNode(ISD::FP_ROUND, dl, ST->getMemoryVT(), Val, in SoftenFloatOp_STORE()
1898 case ISD::FP_ROUND: Res = ExpandFloatOp_FP_ROUND(N); break; in ExpandFloatOperand()
2008 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ExpandFloatOp_FP_ROUND()
2441 case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break; in PromoteFloatResult()
2722 DAG.getNode(ISD::FP_ROUND, DL, VT, NV, in PromoteFloatRes_XINT_TO_FP()
2806 case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp3202 case ISD::FP_ROUND: { in ExpandNode()
4743 case ISD::FP_ROUND: in ConvertNodeToLibcall()
5129 TruncOp = ISD::FP_ROUND; in PromoteNode()
5138 if (TruncOp != ISD::FP_ROUND) in PromoteNode()
5198 Tmp1 = DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp1, in PromoteNode()
5266 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp3, in PromoteNode()
5295 DAG.getNode(ISD::FP_ROUND, dl, OVT, in PromoteNode()
5329 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp3, in PromoteNode()
5348 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp2, in PromoteNode()
5376 DAG.getNode(ISD::FP_ROUND, dl, OVT, Tmp2, in PromoteNode()
[all …]
H A DLegalizeVectorOps.cpp413 case ISD::FP_ROUND: in LegalizeOp()
608 Res = DAG.getNode(ISD::FP_ROUND, DL, ScalarVT, Res, in PromoteReduction()
730 case ISD::FP_ROUND: in Promote()
772 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, in Promote()
H A DLegalizeVectorTypes.cpp59 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
382 return DAG.getNode(ISD::FP_ROUND, DL, in ScalarizeVecRes_FP_ROUND()
714 case ISD::FP_ROUND: in ScalarizeVectorOperand()
890 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), in ScalarizeVecOp_FP_ROUND()
1096 case ISD::FP_ROUND: in SplitVectorResult()
2321 if (Opcode == ISD::FP_ROUND) { in SplitVecRes_UnaryOp()
2985 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break; in SplitVectorOperand()
3912 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec, in SplitVecOp_TruncateHelper()
4240 case ISD::FP_ROUND: in WidenVectorResult()
6070 case ISD::FP_ROUND: in WidenVectorOperand()
[all …]
H A DSelectionDAGDumper.cpp360 case ISD::FP_ROUND: return "fp_round"; in getOperationName()
H A DDAGCombiner.cpp13069 CastOpcode == ISD::FP_ROUND) && in matchVSelectOpSizesWithSetCC()
13095 if (CastOpcode == ISD::FP_ROUND) { in matchVSelectOpSizesWithSetCC()
17071 } else if (N1.getOpcode() == ISD::FP_ROUND && in visitFDIV()
17221 N1.getOpcode() != ISD::FP_ROUND) in CanCombineFCOPYSIGN_EXTEND_ROUND()
17572 if (N0.getOpcode() == ISD::FP_ROUND) { in visitFP_ROUND()
17577 if (!hasOperation(ISD::FP_ROUND, VT)) in visitFP_ROUND()
17598 ISD::FP_ROUND, DL, VT, N0.getOperand(0), in visitFP_ROUND()
17634 N->use_begin()->getOpcode() == ISD::FP_ROUND) in visitFP_EXTEND()
17648 if (N0.getOpcode() == ISD::FP_ROUND in visitFP_EXTEND()
17653 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, in visitFP_EXTEND()
[all …]
H A DSelectionDAG.cpp1432 : getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtendOrRound()
5161 case ISD::FP_ROUND: { in isKnownNeverNaN()
5652 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node"); in getNode()
6475 if (N1CFP && Opcode == ISD::FP_ROUND) { in foldConstantFPMath()
6738 case ISD::FP_ROUND: in getNode()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2487 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f32, 1 }, in getCastInstrCost()
2488 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f32, 1 }, in getCastInstrCost()
2489 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f32, 3 }, in getCastInstrCost()
2492 { ISD::FP_ROUND, MVT::nxv2f16, MVT::nxv2f64, 1 }, in getCastInstrCost()
2493 { ISD::FP_ROUND, MVT::nxv4f16, MVT::nxv4f64, 3 }, in getCastInstrCost()
2494 { ISD::FP_ROUND, MVT::nxv8f16, MVT::nxv8f64, 7 }, in getCastInstrCost()
2497 { ISD::FP_ROUND, MVT::nxv2f32, MVT::nxv2f64, 1 }, in getCastInstrCost()
2498 { ISD::FP_ROUND, MVT::nxv4f32, MVT::nxv4f64, 3 }, in getCastInstrCost()
2499 { ISD::FP_ROUND, MVT::nxv8f32, MVT::nxv8f64, 6 }, in getCastInstrCost()
H A DAArch64ISelLowering.cpp544 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); in AArch64TargetLowering()
545 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in AArch64TargetLowering()
546 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in AArch64TargetLowering()
1479 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1586 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Custom); in AArch64TargetLowering()
1592 setOperationAction(ISD::FP_ROUND, VT, Custom); in AArch64TargetLowering()
1886 setOperationAction(ISD::FP_ROUND, VT, Custom); in addTypeForFixedLengthSVE()
4294 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, in LowerVectorINT_TO_FP()
4342 ISD::FP_ROUND, dl, MVT::f16, in LowerINT_TO_FP()
6102 Final = DAG.getNode(ISD::FP_ROUND, DL, XScalarTy, Final, in LowerFLDEXP()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp590 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
591 {ISD::FP_ROUND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
630 ((ISD == ISD::FP_ROUND && SrcTy.getScalarType() == MVT::f64 && in getCastInstrCost()
636 {ISD::FP_ROUND, MVT::v2f64, 2}, in getCastInstrCost()
824 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp181 ISD::FP_ROUND, ISD::CONCAT_VECTORS}); in WebAssemblyTargetLowering()
2567 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2608 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2652 case ISD::FP_ROUND: in performVectorTruncZeroCombine()
2882 case ISD::FP_ROUND: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2625 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2670 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2805 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2955 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
3321 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerUINT_TO_FP()
3334 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerUINT_TO_FP()
3367 return DAG.getNode(ISD::FP_ROUND, SL, MVT::bf16, ToF32, FPRoundFlag); in LowerSINT_TO_FP()
3383 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag); in LowerSINT_TO_FP()
4857 case ISD::FP_ROUND: { in performFNegCombine()
4862 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
[all …]
H A DR600ISelLowering.cpp201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
1725 case ISD::FP_ROUND: { in PerformDAGCombine()
H A DSIISelLowering.cpp222 setOperationAction(ISD::FP_ROUND, MVT::bf16, Expand); in SITargetLowering()
287 setOperationAction(ISD::FP_ROUND, in SITargetLowering()
598 setOperationAction({ISD::FP_ROUND, ISD::STRICT_FP_ROUND, ISD::FCOS, in SITargetLowering()
916 setTargetDAGCombine(ISD::FP_ROUND); in SITargetLowering()
5571 case ISD::FP_ROUND: in LowerOperation()
6256 DAG.getNode(ISD::FP_ROUND, DL, VT, Op, in getFPExtOrFPRound()
6270 if (Op.getOpcode() != ISD::FP_ROUND) in lowerFP_ROUND()
10785 return DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Sqrt, in lowerFSQRTF16()
11043 Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt, in performUCharToFloatCombine()
12361 case ISD::FP_ROUND: in isCanonicalized()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1909 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1937 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1938 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
3293 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp882 case ISD::FP_ROUND: in getCastInstrCost()
H A DRISCVISelLowering.cpp458 setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom); in RISCVTargetLowering()
941 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1029 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1246 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
1297 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
6066 return DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, Powi, in LowerOperation()
6095 case ISD::FP_ROUND: { in LowerOperation()
6105 DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, Op0, in LowerOperation()
6131 return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NC, in LowerOperation()
6433 return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NewSplat, in LowerOperation()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1113 case ISD::FP_ROUND: in PreprocessISelDAG()
1127 case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break; in PreprocessISelDAG()
1342 case ISD::FP_ROUND: in PreprocessISelDAG()
1373 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
H A DX86ISelLoweringCall.cpp1162 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, in LowerCallResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1231 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1232 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1282 setOperationAction(ISD::FP_ROUND, VT, Custom); in PPCTargetLowering()
8815 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8896 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
9193 (V->getOperand(i).getOpcode() == ISD::FP_ROUND && in haveEfficientBuildVectorPattern()
11668 case ISD::FP_ROUND: in LowerOperation()
14514 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
14559 if (FirstInput.getOpcode() == ISD::FP_ROUND && in combineBVOfConsecutiveLoads()
15000 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in combineFPToIntToFP()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp185 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
188 setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); in initializeHVXLowering()
1578 : DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV, in resizeToWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1885 case FPTrunc: return ISD::FP_ROUND; in InstructionOpcodeToISD()

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