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Searched refs:FPR8 (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp322 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID]; in isFpOrNEON() local
329 FPR16.contains(Reg) || FPR8.contains(Reg); in isFpOrNEON()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td436 def FPR8 : RegisterClass<"AArch64", [i8], 8, (sequence "B%u", 0, 31)> {
679 def FPR8Op : RegisterOperand<FPR8, "printOperand"> {
680 let ParserMatchClass = FPRAsmOperand<"FPR8">;
H A DAArch64InstrFormats.td7370 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;
7636 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
7651 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
7666 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
7737 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
7739 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
8304 def i8 : BaseSIMDScalarDUP<FPR8, V128, asm, ".b", VectorIndexB> {
8332 FPR8, V128, VectorIndexB>;
9744 FPR8, FPR16, vecshiftR8, asm, []> {
9763 FPR8, FPR8, vecshiftL8, asm, []> {
[all …]
H A DSVEInstrFormats.td6916 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>;
7025 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>;
7233 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
7239 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
H A DAArch64InstrInfo.td9433 …defm STLURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b00, FPR8 , (outs), (ins FPR8 :$Rt, GPR64…
9438 …defm LDAPURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b01, FPR8 , (outs FPR8 :$Rt), (ins GPR64s…