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Searched refs:FPR64 (Results 1 – 25 of 26) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td259 def : Pat<(fma FPR64:$fj, FPR64:$fk, FPR64:$fa), (FMADD_D $fj, $fk, $fa)>;
262 def : Pat<(fma FPR64:$fj, FPR64:$fk, (fneg FPR64:$fa)),
263 (FMSUB_D FPR64:$fj, FPR64:$fk, FPR64:$fa)>;
266 def : Pat<(fneg (fma FPR64:$fj, FPR64:$fk, FPR64:$fa)),
267 (FNMADD_D FPR64:$fj, FPR64:$fk, FPR64:$fa)>;
270 def : Pat<(fma_nsz (fneg FPR64:$fj), FPR64:$fk, (fneg FPR64:$fa)),
271 (FNMADD_D FPR64:$fj, FPR64:$fk, FPR64:$fa)>;
274 def : Pat<(fneg (fma FPR64:$fj, FPR64:$fk, (fneg FPR64:$fa))),
275 (FNMSUB_D FPR64:$fj, FPR64:$fk, FPR64:$fa)>;
278 def : Pat<(fma_nsz (fneg FPR64:$fj), FPR64:$fk, FPR64:$fa),
[all …]
H A DLoongArchFloatInstrFormats.td19 // Some FP instructions are defined twice, for accepting FPR32 and FPR64, but
H A DLoongArchRegisterInfo.td171 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
H A DLoongArchLASXInstrInfo.td1553 def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm),
1554 (XVINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm2:$imm)>;
1581 def : Pat<(lasxsplatf64 FPR64:$fj),
1582 (XVREPLVE0_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64))>;
H A DLoongArchLSXInstrInfo.td1651 def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm),
1652 (VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>;
1688 def : Pat<(lsxsplatf64 FPR64:$fj),
1689 (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td188 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
189 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
292 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
296 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
297 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
300 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
301 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
304 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
305 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
308 def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
[all …]
H A DRISCVInstrInfoZfa.td110 def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
112 def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,
175 (FLTQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
177 (FLEQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
219 def: Pat<(any_frint FPR64:$rs1), (FROUNDNX_D FPR64:$rs1, FRM_DYN)>;
222 def: Pat<(any_fnearbyint FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_DYN)>;
224 def: Pat<(any_fround FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RMM)>;
225 def: Pat<(any_froundeven FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RNE)>;
226 def: Pat<(any_ffloor FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RDN)>;
227 def: Pat<(any_fceil FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RUP)>;
[all …]
H A DRISCVInstrInfoZfh.td46 ?, ?, FPR32, FPR64, FPR16>;
48 ?, ?, FPR32, FPR64, FPR16>;
567 def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>;
571 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)),
573 def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>;
H A DRISCVInstrInfoXTHead.td439 def TH_FLRD : THLoadIndexed<FPR64, 0b01100, "th.flrd">,
441 def TH_FSRD : THStoreIndexed<FPR64, 0b01100, "th.fsrd">,
455 def TH_FLURD : THLoadIndexed<FPR64, 0b01110, "th.flurd">,
457 def TH_FSURD : THStoreIndexed<FPR64, 0b01110, "th.fsurd">,
864 defm : StIdxPat<store, TH_FSRD, FPR64, f64>;
874 defm : StZextIdxPat<store, TH_FSURD, FPR64, f64>;
H A DRISCVInstrInfoC.td508 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
566 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
976 def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
977 (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
1018 def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
1019 (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
H A DRISCVInstrInfoXSf.td554 !eq(Sew, 64) : FPR64);
558 !eq(Scalar, f64) : "FPR64");
H A DRISCVRegisterInfo.td252 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
H A DRISCVInstrInfoVPseudos.td118 ["FPR64", "F"],
278 !eq(Scal, f64) : "FPR64");
332 def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, V_M1, f64, FPR64>;
351 V_M2, f64, FPR64>;
353 V_M4, f64, FPR64>;
355 V_M8, f64, FPR64>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4768 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
4769 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
4780 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
4781 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5536 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5538 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5540 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5546 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5550 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5554 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
[all …]
H A DAArch64InstrFormats.td5470 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
5516 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
7361 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
7367 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
7372 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
7400 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
7418 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
7595 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
7647 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
9015 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
[all …]
H A DAArch64RegisterInfo.td447 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
453 64, (trunc FPR64, 16)>;
478 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
480 [(rotl FPR64, 0), (rotl FPR64, 1),
481 (rotl FPR64, 2)]>;
483 [(rotl FPR64, 0), (rotl FPR64, 1),
484 (rotl FPR64, 2), (rotl FPR64, 3)]>;
525 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
667 defm VecListOne : VectorList<1, FPR64, FPR128>;
695 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
[all …]
H A DAArch64InstrGISel.td323 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
324 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
325 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
H A DAArch64FrameLowering.cpp2757 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2768 case FPR64: in getScale()
2827 RPI.Type = RegPairInfo::FPR64; in computeCalleeSaveRegisterPairs()
2849 case RegPairInfo::FPR64: in computeCalleeSaveRegisterPairs()
3028 case RegPairInfo::FPR64: in spillCalleeSavedRegisters()
3132 case RegPairInfo::FPR64: in restoreCalleeSavedRegisters()
H A DAArch64SVEInstrInfo.td794 def : Pat<(nxv2f64 (splat_vector (f64 FPR64:$src))),
795 (DUP_ZZI_D (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), 0)>;
3082 def : Pat<(nxv2i64 (vector_insert (nxv2i64 (undef)), (i64 FPR64:$src), 0)),
3083 (INSERT_SUBREG (nxv2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
3101 def : Pat<(nxv2f64 (vector_insert (nxv2f64 (undef)), (f64 FPR64:$src), 0)),
3102 (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
3120 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), 0)),
3121 (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>;
3198 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), GPR64:$index)),
H A DAArch64SMEInstrInfo.td208 …defm _FPR64 : CoalescerBarrierPseudo<FPR64, [f64, v8i8, v4i16, v2i32, v1i64, v4f16, v2f32, v1f64,…
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td210 class FPR64<bits<16> num, string n, FPR32 high>
217 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
227 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
232 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
237 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
238 !cast<FPR64>("F"#I#"D")>;
252 // A full 128-bit vector register, with an FPR64 as its high part.
253 class VR128<bits<16> num, string n, FPR64 high>
261 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBanks.td16 def FPRBRegBank : RegisterBank<"FPRB", [FPR64]>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp319 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; in isFpOrNEON() local
328 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
H A DCSKYInstrInfoF2.td26 let MIOperandInfo = (ops FPR64, uimm5);
30 def FPR64Op : RegisterOperand<FPR64, "printFPR">;

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