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Searched refs:FP64 (Results 1 – 19 of 19) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td23 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>;
79 def TBDR : BinaryRRFe<"tbdr", 0xB351, FP64, FP64>;
90 def LCDR : UnaryRR <"lcdr", 0x23, null_frag, FP64, FP64>;
110 def HDR : UnaryRR <"hdr", 0x24, null_frag, FP64, FP64>;
114 def SQDR : UnaryRRE<"sqdr", 0xB244, null_frag, FP64, FP64>;
122 def FIDR : UnaryRRE<"fidr", 0xB37F, null_frag, FP64, FP64>;
134 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
145 def AWR : BinaryRR<"awr", 0x2E, null_frag, FP64, FP64>;
154 def SDR : BinaryRR<"sdr", 0x2B, null_frag, FP64, FP64>;
164 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
[all …]
H A DSystemZInstrDFP.td147 def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;
151 def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;
158 def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;
161 def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;
169 def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;
173 def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;
180 def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;
183 def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;
190 def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;
196 def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
[all …]
H A DSystemZInstrFP.td46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
59 def LTDBR : UnaryRRE<"ltdbr", 0xB312, null_frag, FP64, FP64>;
97 def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;
333 def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>;
344 def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>;
355 def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>;
373 def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>;
380 def : Pat<(any_frint FP64:$src), (FIDBR 0, FP64:$src)>;
388 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>;
441 def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64, FP64>;
[all …]
H A DSystemZRegisterInfo.td244 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
H A DSystemZInstrVector.td1803 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_h64>;
1809 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1810 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1812 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1813 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
/freebsd-14.2/contrib/llvm-project/clang/lib/Basic/Targets/
H A DMips.cpp143 case FP64: in getTargetDefines()
148 if (FPMode == FP64 || IsSingleFloat) in getTargetDefines()
221 .Case("fp64", FPMode == FP64) in hasFeature()
259 if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat && in validateTarget()
265 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" || in validateTarget()
271 if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" || in validateTarget()
H A DMips.h59 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator
318 FPMode = isFP64Default() ? FP64 : FPXX; in handleTargetFeatures()
340 FPMode = FP64; in handleTargetFeatures()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td31 def FP64 : WebAssemblyReg<"%FP64">;
63 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
H A DWebAssemblyRegisterInfo.cpp48 WebAssembly::FP64}) in getReservedRegs()
148 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
H A DWebAssemblyFrameLowering.cpp189 ? WebAssembly::FP64 in getFPReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.h119 bool FP64) const;
122 bool FP64) const;
H A DMipsSEFrameLowering.cpp85 MachineBasicBlock::iterator I, bool FP64) const;
87 MachineBasicBlock::iterator I, bool FP64) const;
288 bool FP64) const { in expandBuildPairF64()
319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
344 bool FP64) const { in expandExtractElementF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
H A DMipsSEInstrInfo.cpp754 bool FP64) const { in expandExtractElementF64()
786 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) in expandExtractElementF64()
787 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), in expandExtractElementF64()
796 bool isMicroMips, bool FP64) const { in expandBuildPairF64()
842 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) in expandBuildPairF64()
843 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), in expandBuildPairF64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUFeatures.td10 "FP64",
H A DR600Subtarget.h39 bool FP64 = false; variable
H A DGCNSubtarget.h100 bool FP64 = false; variable
340 return FP64; in hasFP64()
348 return FP64; in hasHWFP64()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64.td460 "true", "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE]>;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2654 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions
/freebsd-14.2/share/misc/
H A Dpci_vendors15409 1148 5841 FDDI SK-5841 (SK-NET FDDI-FP64)