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Searched refs:FP (Results 1 – 25 of 279) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp465 if (BB == FP.SplitB || BB == FP.TrueB || BB == FP.FalseB) in computePhiCost()
508 if (MBPI && FP.TrueB && !FP.FalseB && in isProfitable()
513 if (MBPI && !FP.TrueB && FP.FalseB && in isProfitable()
518 if (FP.TrueB && FP.FalseB) { in isProfitable()
570 TotalPh = computePhiCost(FP.JoinB, FP); in isProfitable()
865 predicateBlockNB(FP.SplitB, OldTI, FP.TrueB, FP.PredR, true); in convert()
870 predicateBlockNB(FP.SplitB, At, FP.FalseB, FP.PredR, false); in convert()
877 FP.SplitB->erase(OldTI, FP.SplitB->end()); in convert()
894 if (T != FP.TrueB && T != FP.FalseB) { in convert()
909 FP.SplitB->addSuccessor(FP.JoinB); in convert()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleV6.td227 // Single-precision FP ALU
230 // Double-precision FP ALU
239 // Single-precision FP MAC
242 // Double-precision FP MAC
251 // Single-precision FP DIV
254 // Double-precision FP DIV
257 // Single-precision FP SQRT
260 // Double-precision FP SQRT
275 // Single-precision FP Load
281 // FP Load Multiple
[all …]
H A DARMScheduleA8.td302 // Single-precision FP ALU
306 // Double-precision FP ALU
320 // Single-precision FP MAC
324 // Double-precision FP MAC
338 // Single-precision FP DIV
343 // Double-precision FP DIV
348 // Single-precision FP SQRT
392 // FP Load Multiple
421 // FP Store Multiple
778 // Quad-register FP Unary
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN1.td404 // FP arithmetic
405 // FP min/max
406 // FP negate
407 // FP select
410 // FP compare
413 // FP divide
414 // FP square root
431 // FP multiply
455 // FP move, immed
666 // ASIMD FP compare
[all …]
H A DAArch64SchedNeoverseV1.td656 // FP arithmetic
657 // FP min/max
658 // FP negate
661 // FP compare
664 // FP divide
665 // FP square root
682 // FP multiply
692 // FP select
711 // FP move, immed
892 // ASIMD FP compare
[all …]
H A DAArch64SchedThunderX3T110.td1201 // FP absolute value
1202 // FP min/max
1203 // FP negate
1209 // FP arithmetic
1212 // FP compare
1218 // FP Mul, Div, Sqrt
1254 // FP divide, S-form
1270 // FP multiply
1298 // FP select
1313 // FP move, immed
[all …]
H A DAArch64SchedThunderX2T99.td40 // Port 0: ALU, FP/SIMD.
1093 // FP absolute value
1094 // FP min/max
1095 // FP negate
1101 // FP arithmetic
1104 // FP compare
1110 // FP Mul, Div, Sqrt
1162 // FP multiply
1190 // FP select
1205 // FP move, immed
[all …]
H A DAArch64SchedNeoverseN2.td788 // FP absolute value
789 // FP arithmetic
790 // FP min/max
791 // FP negate
792 // FP select
795 // FP compare
801 // FP divide, H-form
815 // FP multiply
838 // FP move, immed
1054 // ASIMD FP compare
[all …]
H A DAArch64SchedExynosM3.td45 def M3PipeF0 : ProcResource<1>; // FP #0
237 // FP data instructions.
244 // FP miscellaneous instructions.
249 // FP load instructions.
252 // FP store instructions.
257 // ASIMD FP instructions.
536 // FP data instructions.
551 // FP miscellaneous instructions.
565 // FP load instructions.
588 // FP store instructions.
[all …]
H A DAArch64SchedNeoverseV2.td1278 // FP absolute value
1279 // FP arithmetic
1280 // FP min/max
1281 // FP negate
1282 // FP select
1285 // FP compare
1291 // FP divide, H-form
1305 // FP multiply
1333 // FP move, immed
1542 // ASIMD FP compare
[all …]
H A DAArch64SchedA57.td445 // ASIMD FP arith, normal, D-form
455 // ASIMD FP compare, D-form
457 // ASIMD FP compare, Q-form
467 // ASIMD FP divide, D-form, F32
469 // ASIMD FP divide, Q-form, F32
471 // ASIMD FP divide, Q-form, F64
490 // ASIMD FP max/min, reduce
493 // ASIMD FP multiply, D-form, FZ
495 // ASIMD FP multiply, Q-form, FZ
511 // ASIMD FP round, D-form
[all …]
H A DAArch64SchedA64FX.td1251 // FP absolute value
1252 // FP min/max
1253 // FP negate
1259 // FP arithmetic
1264 // FP compare
1270 // FP Div, Sqrt
1295 // FP divide, S-form
1304 // FP divide, D-form
1317 // FP select
1332 // FP move, immed
[all …]
H A DAArch64CallingConvention.td257 // The first 4 FP/Vector arguments are passed in XMM registers.
521 // We put FP before LR, so that frame lowering logic generates (FP,LR) pairs,
522 // and not (LR,FP) pairs.
564 LR, FP)>;
572 LR, FP)>;
576 LR, FP)>;
597 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
602 (sequence "X%u", 0, 28), FP, LR, SP,
617 (sequence "X%u", 18, 28), FP, SP,
654 FP,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetOptionsImpl.cpp32 StringRef FP = F.getFnAttribute("frame-pointer").getValueAsString(); in DisableFramePointerElim() local
33 if (FP == "all") in DisableFramePointerElim()
35 if (FP == "non-leaf") in DisableFramePointerElim()
37 if (FP == "none") in DisableFramePointerElim()
H A DRegisterUsageInfo.cpp58 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
59 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
63 PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) { in getRegUsageInfo() argument
64 auto It = RegMasks.find(&FP); in getRegUsageInfo()
/freebsd-14.2/crypto/openssl/crypto/sha/asm/
H A Dkeccak1600-c64x.pl105 STDW A3:A2,*FP[-7]
410 || STDW A13:A12,*FP[-4]
412 || STDW A11:A10,*FP[-5]
414 || STW A14,*FP[-6]
524 || LDW *FP[-6],A14
563 || STW A14,*FP[-6]
722 || LDW *FP[-6],A14
765 || STW A14,*FP[-2]
766 STDW A13:A12,*FP[-2]
838 LDDW *FP[-2],A13:A12
[all …]
/freebsd-14.2/sys/arm/arm/
H A Ddb_trace.c86 state->registers[SP], state->registers[FP]); in db_stack_trace_cmd()
90 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); in db_stack_trace_cmd()
145 state.registers[FP] = ctx->pcb_regs.sf_r11; in db_trace_thread()
165 state.registers[FP] = (uint32_t)__builtin_frame_address(0); in db_trace_self()
/freebsd-14.2/contrib/llvm-project/clang/lib/AST/Interp/
H A DEvaluationResult.cpp25 else if (const auto *FP = std::get_if<FunctionPointer>(&Value)) in toAPValue() local
26 return FP->toAPValue(); in toAPValue()
48 else if (const auto *FP = std::get_if<FunctionPointer>(&Value)) // Nope in toRValue() local
49 return FP->toAPValue(); in toRValue()
184 else if (const auto *FP = std::get_if<FunctionPointer>(&Value)) // Nope in dump() local
185 FP->toAPValue().printPretty(OS, ASTCtx, SourceType); in dump()
H A DPointer.cpp265 const Pointer &FP = Ptr.atField(F.Offset); in toRValue() local
267 if (FP.isActive()) { in toRValue()
269 TYPE_SWITCH(*T, Value = FP.deref<T>().toAPValue()); in toRValue()
271 Ok &= Composite(FieldTy, FP, Value); in toRValue()
287 const Pointer &FP = Ptr.atField(FD->Offset); in toRValue() local
291 TYPE_SWITCH(*T, Value = FP.deref<T>().toAPValue()); in toRValue()
293 Ok &= Composite(FieldTy, FP, Value); in toRValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiFrameLowering.cpp111 .addReg(Lanai::FP) in emitPrologue()
119 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP) in emitPrologue()
184 .addReg(Lanai::FP) in emitEpilogue()
188 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP) in emitEpilogue()
189 .addReg(Lanai::FP) in emitEpilogue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DLegacyPassManager.cpp301 return FP; in getContainedManager()
1393 FP->dumpPassStructure(Offset + 1); in dumpPassStructure()
1394 dumpLastUses(FP, Offset+1); in dumpPassStructure()
1430 "RunPass", [FP]() { return std::string(FP->getPassName()); }); in runOnFunction()
1433 dumpRequiredSet(FP); in runOnFunction()
1435 initializeAnalysisImpl(FP); in runOnFunction()
1472 dumpPreservedSet(FP); in runOnFunction()
1473 dumpUsedSet(FP); in runOnFunction()
1475 verifyPreservedAnalysis(FP); in runOnFunction()
1477 removeNotPreservedAnalysis(FP); in runOnFunction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp268 static std::string toString(const APFloat &FP) { in toString() argument
270 if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) && in toString()
271 !FP.bitwiseIsEqual( in toString()
272 APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) { in toString()
273 APInt AI = FP.bitcastToAPInt(); in toString()
284 auto Written = FP.convertToHexString( in toString()
/freebsd-14.2/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-c64xplus.pl116 || [A2] STDW A13:A12,*FP[-3]
117 [A2] STDW A11:A10,*FP[-4]
251 LDDW *FP[-4],A11:A10 ; ABI says so
252 LDDW *FP[-3],A13:A12
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp195 Reserved.set(Mips::FP); in getReservedRegs()
280 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : in getFrameRegister()
296 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; in canRealignStack() local
305 if (!MF.getRegInfo().canReserveReg(FP)) in canRealignStack()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterUsageInfo.h51 void storeUpdateRegUsageInfo(const Function &FP,
56 ArrayRef<uint32_t> getRegUsageInfo(const Function &FP);

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