| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 89 DAG_FUNCTION(nearbyint, 1, 1, experimental_constrained_nearbyint, FNEARBYINT)
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| H A D | VPIntrinsics.def | 437 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEARBYINT)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 953 FNEARBYINT, enumerator
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| H A D | BasicTTIImpl.h | 1935 ISD = ISD::FNEARBYINT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 217 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 104 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
1333 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
2412 case ISD::FNEARBYINT: in PromoteFloatResult()
2820 case ISD::FNEARBYINT: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 409 case ISD::FNEARBYINT: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 96 case ISD::FNEARBYINT: in ScalarizeVectorResult()
1089 case ISD::FNEARBYINT: in SplitVectorResult()
4279 case ISD::FNEARBYINT: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4493 case ISD::FNEARBYINT: in ConvertNodeToLibcall()
5357 case ISD::FNEARBYINT: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 6497 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in visitIntrinsicCall()
8858 if (visitUnaryFloatCall(I, ISD::FNEARBYINT)) in visitCall()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 354 setOperationAction(ISD::FNEARBYINT, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
485 ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
616 case ISD::FNEARBYINT: in fnegFoldsIntoOpcode()
1344 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
4834 case ISD::FNEARBYINT: // XXX - Should fround be handled? in performFNegCombine()
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| H A D | AMDGPUISelDAGToDAG.cpp | 166 case ISD::FNEARBYINT: in fp16SrcZerosHighBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 936 ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 316 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
859 setOperationAction(ISD::FNEARBYINT, VT, Expand); in PPCTargetLowering()
921 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1012 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
1013 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
1019 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
1025 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1228 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 494 setOperationAction(ISD::FNEARBYINT, MVT::f16, in RISCVTargetLowering()
539 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in RISCVTargetLowering()
552 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in RISCVTargetLowering()
918 ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SETCC, ISD::FMAXIMUM, in RISCVTargetLowering()
952 ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT, in RISCVTargetLowering()
1300 ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT}, in RISCVTargetLowering()
2951 case ISD::FNEARBYINT: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
6354 case ISD::FNEARBYINT: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 446 case ISD::FNEARBYINT: in NVPTXTargetLowering()
763 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in NVPTXTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1206 case ISD::FNEARBYINT: in PreprocessISelDAG()
1224 case ISD::FNEARBYINT: Imm = 0xC; break; in PreprocessISelDAG()
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| H A D | X86ISelLowering.cpp | 575 setOperationAction(ISD::FNEARBYINT, VT, Action); in X86TargetLowering()
791 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand); in X86TargetLowering()
925 setOperationAction(ISD::FNEARBYINT, VT, Expand); in X86TargetLowering()
1270 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal); in X86TargetLowering()
1380 setOperationAction(ISD::FNEARBYINT, VT, Legal); in X86TargetLowering()
1812 setOperationAction(ISD::FNEARBYINT, VT, Legal); in X86TargetLowering()
2120 setOperationAction(ISD::FNEARBYINT, VT, Legal); in X86TargetLowering()
43925 case ISD::FNEARBYINT: in scalarizeExtEltFP()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 129 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 701 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
740 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); in AArch64TargetLowering()
751 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); in AArch64TargetLowering()
768 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
1084 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1241 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1471 setOperationAction(ISD::FNEARBYINT, VT, Custom); in AArch64TargetLowering()
1883 setOperationAction(ISD::FNEARBYINT, VT, Custom); in addTypeForFixedLengthSVE()
6181 case ISD::FNEARBYINT: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 506 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
566 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in SystemZTargetLowering()
607 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 375 setOperationAction(ISD::FNEARBYINT, VT, Expand); in addMVEVectorTypes()
889 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
910 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
927 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
1069 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
1514 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1530 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 521 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 141 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1637 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
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