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Searched refs:FMAXNUM (Results 1 – 25 of 32) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3586 { ISD::FMAXNUM, MVT::f32, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3587 { ISD::FMAXNUM, MVT::v4f32, { 1, 1, 3, 3 } }, in getIntrinsicInstrCost()
3588 { ISD::FMAXNUM, MVT::v8f32, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3589 { ISD::FMAXNUM, MVT::v16f32, { 4, 4, 3, 3 } }, in getIntrinsicInstrCost()
3590 { ISD::FMAXNUM, MVT::f64, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3591 { ISD::FMAXNUM, MVT::v2f64, { 1, 1, 3, 3 } }, in getIntrinsicInstrCost()
3592 { ISD::FMAXNUM, MVT::v4f64, { 2, 2, 3, 3 } }, in getIntrinsicInstrCost()
3593 { ISD::FMAXNUM, MVT::v8f64, { 3, 3, 3, 3 } }, in getIntrinsicInstrCost()
3922 { ISD::FMAXNUM, MVT::f64, { 5, 5, 7, 7 } }, in getIntrinsicInstrCost()
4092 ISD = ISD::FMAXNUM; in getIntrinsicInstrCost()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def85 DAG_FUNCTION(maxnum, 2, 0, experimental_constrained_maxnum, FMAXNUM)
H A DVPIntrinsics.def380 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAXNUM)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h970 FMAXNUM, enumerator
H A DBasicTTIImpl.h1914 ISD = ISD::FMAXNUM; in getTypeBasedIntrinsicInstrCost()
H A DTargetLowering.h2790 case ISD::FMAXNUM: in isCommutativeBinOp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp192 case ISD::FMAXNUM: return "fmaxnum"; in getOperationName()
H A DLegalizeFloatTypes.cpp75 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
1304 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi); break; in ExpandFloatResult()
2427 case ISD::FMAXNUM: in PromoteFloatResult()
2836 case ISD::FMAXNUM: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp386 case ISD::FMAXNUM: in LegalizeOp()
1035 case ISD::FMAXNUM: in Expand()
H A DSelectionDAG.cpp466 return ISD::FMAXNUM; in getVecReduceBaseOpcode()
5181 case ISD::FMAXNUM: { in isKnownNeverNaN()
6466 case ISD::FMAXNUM: in foldConstantFPMath()
11589 case ISD::FMAXNUM: { in isNeutralConstant()
11598 if (Opcode == ISD::FMAXNUM) in isNeutralConstant()
12847 case ISD::FMAXNUM: { in getNeutralElement()
12853 if (Opcode == ISD::FMAXNUM) in getNeutralElement()
H A DSelectionDAGBuilder.cpp3571 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; in visitSelect()
3573 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) || in visitSelect()
3575 TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()))) in visitSelect()
3576 Opc = ISD::FMAXNUM; in visitSelect()
6533 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl, in visitIntrinsicCall()
8825 if (visitBinaryFloatCall(I, ISD::FMAXNUM)) in visitCall()
H A DLegalizeDAG.cpp3564 case ISD::FMAXNUM: { in ExpandNode()
4407 case ISD::FMAXNUM: in ConvertNodeToLibcall()
5257 case ISD::FMAXNUM: in PromoteNode()
H A DLegalizeVectorTypes.cpp129 case ISD::FMAXNUM: in ScalarizeVectorResult()
1144 case ISD::FMAXNUM: case ISD::VP_FMAXNUM: in SplitVectorResult()
4134 case ISD::FMAXNUM: case ISD::VP_FMAXNUM: in WidenVectorResult()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp209 ISD::FREM, ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in SITargetLowering()
759 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, in SITargetLowering()
890 ISD::FMAXNUM, in SITargetLowering()
5602 case ISD::FMAXNUM: in LowerOperation()
8032 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
12397 case ISD::FMAXNUM: in isCanonicalized()
12729 if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) { in performFCanonicalizeCombine()
12747 case ISD::FMAXNUM: in minMaxOpcToMin3Max3Opc()
12940 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
13117 case ISD::FMAXNUM: in performExtractVectorEltCombine()
[all …]
H A DAMDGPUISelLowering.cpp344 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
479 {ISD::FABS, ISD::FMINNUM, ISD::FMAXNUM, in AMDGPUTargetLowering()
607 case ISD::FMAXNUM: in fnegFoldsIntoOpcode()
4649 case ISD::FMAXNUM: in inverseMinMax()
4652 return ISD::FMAXNUM; in inverseMinMax()
4780 case ISD::FMAXNUM: in performFNegCombine()
H A DAMDGPUISelDAGToDAG.cpp171 case ISD::FMAXNUM: in fp16SrcZerosHighBits()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td777 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
800 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1638 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP, in HexagonTargetLowering()
1770 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1819 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in HexagonTargetLowering()
H A DHexagonISelLoweringHVX.cpp131 setOperationAction(ISD::FMAXNUM, T, Legal); in initializeHVXLowering()
168 setOperationAction(ISD::FMAXNUM, P, Custom); in initializeHVXLowering()
3170 case ISD::FMAXNUM: in LowerHvxOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp831 ISD::FMINNUM, ISD::FMAXNUM, in initActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp613 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in SystemZTargetLowering()
618 setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); in SystemZTargetLowering()
623 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in SystemZTargetLowering()
628 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in SystemZTargetLowering()
633 setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); in SystemZTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp421 ISD::FMINNUM, ISD::FMAXNUM, ISD::LRINT, in RISCVTargetLowering()
445 ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, in RISCVTargetLowering()
914 ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB, in RISCVTargetLowering()
948 setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal); in RISCVTargetLowering()
1293 ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM, in RISCVTargetLowering()
1384 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
5673 case ISD::FMAXNUM: in getRISCVVLOp()
6572 case ISD::FMAXNUM: in LowerOperation()
12208 case ISD::FMAXNUM: in combineBinOpToReduce()
15288 case ISD::FMAXNUM: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp355 setOperationAction(ISD::FMAXNUM, VT, Legal); in addMVEVectorTypes()
794 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); in ARMTargetLowering()
1517 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in ARMTargetLowering()
1520 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal); in ARMTargetLowering()
1522 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1533 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); in ARMTargetLowering()
1574 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal); in ARMTargetLowering()
1576 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); in ARMTargetLowering()
4197 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
10288 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp259 setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, VT, Legal); in initSPUActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp703 ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM, in AArch64TargetLowering()
770 ISD::FROUNDEVEN, ISD::FMINNUM, ISD::FMAXNUM, in AArch64TargetLowering()
1086 ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM, in AArch64TargetLowering()
1463 setOperationAction(ISD::FMAXNUM, VT, Custom); in AArch64TargetLowering()
1747 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM, in addTypeForNEON()
1879 setOperationAction(ISD::FMAXNUM, VT, Custom); in addTypeForFixedLengthSVE()
6350 case ISD::FMAXNUM: in LowerOperation()
20022 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()

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