| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 487 FMAD, enumerator
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| H A D | TargetLowering.h | 3165 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 605 case ISD::FMAD: in fnegFoldsIntoOpcode()
873 case ISD::FMAD: { in getNegatedExpression()
1937 : (unsigned)ISD::FMAD; in LowerDIVREM24()
2023 unsigned FMAD = in LowerUDIVREM64() local
2026 ? (unsigned)ISD::FMAD in LowerUDIVREM64()
2031 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
2040 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
4751 case ISD::FMAD: { in performFNegCombine()
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| H A D | AMDGPUCodeGenPrepare.cpp | 1271 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl() local
1274 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
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| H A D | R600ISelLowering.cpp | 160 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
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| H A D | SIISelLowering.cpp | 481 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
615 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
963 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
12357 case ISD::FMAD: in isCanonicalized()
13296 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
13297 return ISD::FMAD; in getFusedOpcode()
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| H A D | AMDGPUISelDAGToDAG.cpp | 192 case ISD::FMAD: in fp16SrcZerosHighBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 275 case ISD::FMAD: return "fmad"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 2435 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
2844 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
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| H A D | DAGCombiner.cpp | 2011 case ISD::FMAD: return visitFMAD(N); in visit()
15604 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
15608 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFADDForFMACombine()
15834 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
15989 return matcher.match(N, ISD::FMA) || matcher.match(N, ISD::FMAD); in visitFSUBForFMACombine()
16159 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
16926 return DAG.getNode(ISD::FMAD, DL, VT, N0, N1, N2); in visitFMAD()
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| H A D | SelectionDAG.cpp | 5128 case ISD::FMAD: { in isKnownNeverNaN()
7076 case ISD::FMAD: { in getNode()
7087 if (Opcode == ISD::FMAD) { in getNode()
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| H A D | LegalizeDAG.cpp | 3615 case ISD::FMAD: in ExpandNode()
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| H A D | TargetLowering.cpp | 7293 case ISD::FMAD: { in getNegatedExpression()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 1457 if (auto FMAD = in instCombineSVEVectorFAdd() local
1461 return FMAD; in instCombineSVEVectorFAdd()
1477 if (auto FMAD = in instCombineSVEVectorFAddU() local
1481 return FMAD; in instCombineSVEVectorFAddU()
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| H A D | AArch64SchedA510.td | 1083 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_(ZPmZZ|ZPZZZ)_[HSD]")>;
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| H A D | AArch64SchedNeoverseN2.td | 2001 "^(FMAD|FNMAD|FNML[AS]|FN?MSB)_ZPmZZ_[HSD]$")>;
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 360 VP_PROPERTY_FUNCTIONAL_SDOPC(FMAD)
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 834 ISD::FMAD, ISD::SMIN, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 492 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 43905 case ISD::FMAD: in scalarizeExtEltFP()
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