| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 80 DAG_FUNCTION(log2, 1, 1, experimental_constrained_log2, FLOG2)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 945 FLOG2, enumerator
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| H A D | BasicTTIImpl.h | 1902 ISD = ISD::FLOG2; in getTypeBasedIntrinsicInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 230 case ISD::FLOG2: return "flog2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 96 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; in SoftenFloatResult()
1325 case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break; in ExpandFloatResult()
2410 case ISD::FLOG2: in PromoteFloatResult()
2818 case ISD::FLOG2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 399 case ISD::FLOG2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 95 case ISD::FLOG2: in ScalarizeVectorResult()
1088 case ISD::FLOG2: in SplitVectorResult()
4278 case ISD::FLOG2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4445 case ISD::FLOG2: in ConvertNodeToLibcall()
5366 case ISD::FLOG2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5459 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); in expandLog2()
8888 if (visitUnaryFloatCall(I, ISD::FLOG2)) in visitCall()
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| H A D | SelectionDAG.cpp | 5171 case ISD::FLOG2: in isKnownNeverNaN()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 347 setOperationAction(ISD::FLOG2, MVT::f32, Custom); in AMDGPUTargetLowering()
364 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); in AMDGPUTargetLowering()
482 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
1349 case ISD::FLOG2: in LowerOperation()
1387 case ISD::FLOG2: in ReplaceNodeResults()
2757 VT == MVT::f32 ? (unsigned)AMDGPUISD::LOG : (unsigned)ISD::FLOG2; in LowerFLOGUnsafe()
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| H A D | AMDGPUISelDAGToDAG.cpp | 159 case ISD::FLOG2: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 212 ISD::FLDEXP, ISD::FFREXP, ISD::FLOG, ISD::FLOG2, in SITargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 151 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in MipsSETargetLowering()
383 setOperationAction(ISD::FLOG2, Ty, Legal); in addMSAFloatType()
1887 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsISelLowering.cpp | 436 setOperationAction(ISD::FLOG2, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 935 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 250 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 515 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 370 setOperationAction(ISD::FLOG2, VT, Expand); in addMVEVectorTypes()
880 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); in ARMTargetLowering()
902 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); in ARMTargetLowering()
919 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
1061 setOperationAction(ISD::FLOG2, MVT::f64, Expand); in ARMTargetLowering()
1551 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1635 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 685 ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in AArch64TargetLowering()
1502 setOperationAction(ISD::FLOG2, VT, Expand); in AArch64TargetLowering()
1687 setOperationAction(ISD::FLOG2, VT, Expand); in addTypeForNEON()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 498 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
968 setOperationAction(ISD::FLOG2, VT, Expand); in RISCVTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 848 setOperationAction(ISD::FLOG2, VT, Expand); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 568 setOperationAction(ISD::FLOG2, VT, Action); in X86TargetLowering()
882 setOperationAction(ISD::FLOG2, MVT::f80, Expand); in X86TargetLowering()
901 setOperationAction(ISD::FLOG2, VT, Expand); in X86TargetLowering()
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