| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 92 DAG_FUNCTION(ldexp, 2, 1, experimental_constrained_ldexp, FLDEXP)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 937 FLDEXP, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 289 case ISD::FLDEXP: return "fldexp"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 116 case ISD::FLDEXP: in SoftenFloatResult()
1341 case ISD::FLDEXP: in ExpandFloatResult()
2438 case ISD::FLDEXP: R = PromoteFloatRes_ExpOp(N); break; in PromoteFloatResult()
2847 case ISD::FLDEXP: R = SoftPromoteHalfRes_ExpOp(N); break; in SoftPromoteHalfResult()
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| H A D | LegalizeVectorTypes.cpp | 134 case ISD::FLDEXP: in ScalarizeVectorResult()
1004 case ISD::FLDEXP: in SplitVectorResult()
3042 case ISD::FLDEXP: in SplitVectorOperand()
4225 case ISD::FLDEXP: in WidenVectorResult()
6054 case ISD::FLDEXP: in WidenVectorOperand()
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| H A D | LegalizeDAG.cpp | 3585 case ISD::FLDEXP: in ExpandNode()
4517 case ISD::FLDEXP: in ConvertNodeToLibcall()
5316 case ISD::FLDEXP: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 395 case ISD::FLDEXP: in LegalizeOp()
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| H A D | SelectionDAGBuilder.cpp | 6557 setValue(&I, DAG.getNode(ISD::FLDEXP, sdl, in visitIntrinsicCall()
8906 if (visitBinaryFloatCall(I, ISD::FLDEXP)) in visitCall()
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| H A D | LegalizeIntegerTypes.cpp | 1853 case ISD::FLDEXP: in PromoteIntegerOperand()
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| H A D | SelectionDAG.cpp | 5147 case ISD::FLDEXP: { in isKnownNeverNaN()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 212 ISD::FLDEXP, ISD::FFREXP, ISD::FLOG, ISD::FLOG2, in SITargetLowering()
535 setOperationAction({ISD::FLDEXP, ISD::STRICT_FLDEXP}, {MVT::f32, MVT::f64}, in SITargetLowering()
608 setOperationAction({ISD::FLDEXP, ISD::STRICT_FLDEXP}, MVT::f16, Custom); in SITargetLowering()
5604 case ISD::FLDEXP: in LowerOperation()
6331 return DAG.getNode(ISD::FLDEXP, DL, VT, Op.getOperand(0), TruncExp); in lowerFLDEXP()
10914 SDValue SqrtX = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, X, ScaleUp, Flags); in lowerFSQRTF64()
10944 SqrtRet = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, SqrtRet, ScaleDown, Flags); in lowerFSQRTF64()
12363 case ISD::FLDEXP: in isCanonicalized()
14419 case ISD::FLDEXP: in PerformDAGCombine()
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| H A D | AMDGPUISelLowering.cpp | 3041 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3261 return DAG.getNode(ISD::FLDEXP, SL, MVT::f32, FVal, ShAmt); in LowerINT_TO_FP32()
3294 SDValue LdExp = DAG.getNode(ISD::FLDEXP, SL, MVT::f64, CvtHi, in LowerINT_TO_FP64()
5885 case ISD::FLDEXP: in isKnownNeverNaNForTargetNode()
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| H A D | AMDGPUISelDAGToDAG.cpp | 172 case ISD::FLDEXP: in fp16SrcZerosHighBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 878 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 516 def fldexp : SDNode<"ISD::FLDEXP" , SDTFPExpOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1638 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP, in HexagonTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1650 setOperationAction(ISD::FLDEXP, MVT::f64, Custom); in AArch64TargetLowering()
1651 setOperationAction(ISD::FLDEXP, MVT::f32, Custom); in AArch64TargetLowering()
1652 setOperationAction(ISD::FLDEXP, MVT::f16, Custom); in AArch64TargetLowering()
6427 case ISD::FLDEXP: in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 858 setOperationAction(ISD::FLDEXP, VT, Expand); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 584 setOperationAction(ISD::FLDEXP, VT, Action); in X86TargetLowering()
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