Searched refs:FGETSIGN (Results 1 – 8 of 8) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 497 FGETSIGN, enumerator
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 279 case ISD::FGETSIGN: return "fgetsign"; in getOperationName()
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| H A D | TargetLowering.cpp | 2658 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT); in SimplifyDemandedBits()
2659 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); in SimplifyDemandedBits()
2666 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Src); in SimplifyDemandedBits()
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| H A D | SelectionDAG.cpp | 3715 case ISD::FGETSIGN: in computeKnownBits()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 830 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 506 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 667 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); in X86TargetLowering()
668 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); in X86TargetLowering()
31920 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1053 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand); in ARMTargetLowering()
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