| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 75 DAG_FUNCTION(exp2, 1, 1, experimental_constrained_exp2, FEXP2)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 948 FEXP2, enumerator
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| H A D | BasicTTIImpl.h | 1890 ISD = ISD::FEXP2; in getTypeBasedIntrinsicInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 225 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 89 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
1318 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
2406 case ISD::FEXP2: in PromoteFloatResult()
2814 case ISD::FEXP2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 402 case ISD::FEXP2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 90 case ISD::FEXP2: in ScalarizeVectorResult()
1082 case ISD::FEXP2: in SplitVectorResult()
4273 case ISD::FEXP2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4460 case ISD::FEXP2: in ConvertNodeToLibcall()
5370 case ISD::FEXP2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5561 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); in expandExp2()
8894 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| H A D | SelectionDAG.cpp | 5136 case ISD::FEXP2: in isKnownNeverNaN()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 351 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
364 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); in AMDGPUTargetLowering()
481 ISD::FDIV, ISD::FEXP2, ISD::FEXP, in AMDGPUTargetLowering()
1357 case ISD::FEXP2: in LowerOperation()
1396 case ISD::FEXP2: in ReplaceNodeResults()
2852 : (unsigned)ISD::FEXP2, in lowerFEXPUnsafe()
2886 const unsigned Exp2Op = VT == MVT::f32 ? AMDGPUISD::EXP : ISD::FEXP2; in lowerFEXP10Unsafe()
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| H A D | AMDGPUISelDAGToDAG.cpp | 162 case ISD::FEXP2: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 213 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 149 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in MipsSETargetLowering()
382 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1883 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsMSAInstrInfo.td | 2047 // 1.0 when we only need to match ISD::FEXP2.
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 936 ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 251 ISD::FEXP, ISD::FEXP2}) in WebAssemblyTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 512 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 373 setOperationAction(ISD::FEXP2, VT, Expand); in addMVEVectorTypes()
883 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
905 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
922 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
1064 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
1547 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1636 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 443 case ISD::FEXP2: in NVPTXTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 684 ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in AArch64TargetLowering()
1499 setOperationAction(ISD::FEXP2, VT, Expand); in AArch64TargetLowering()
1690 setOperationAction(ISD::FEXP2, VT, Expand); in addTypeForNEON()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 498 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
965 setOperationAction(ISD::FEXP2, VT, Expand); in RISCVTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 850 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 571 setOperationAction(ISD::FEXP2, VT, Action); in X86TargetLowering()
885 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in X86TargetLowering()
904 setOperationAction(ISD::FEXP2, VT, Expand); in X86TargetLowering()
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