| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 1031 { ISD::FDIV, MVT::f32, { 18, 19, 1, 1 } }, // divss in getArithmeticInstrCost()
1032 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps in getArithmeticInstrCost()
1033 { ISD::FDIV, MVT::f64, { 33, 34, 1, 1 } }, // divsd in getArithmeticInstrCost()
1034 { ISD::FDIV, MVT::v2f64, { 65, 66, 1, 1 } }, // divpd in getArithmeticInstrCost()
1049 { ISD::FDIV, MVT::f32, { 17, 19, 1, 1 } }, // divss in getArithmeticInstrCost()
1050 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 6 } }, // divps in getArithmeticInstrCost()
1051 { ISD::FDIV, MVT::f64, { 32, 34, 1, 1 } }, // divsd in getArithmeticInstrCost()
1052 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 6 } }, // divpd in getArithmeticInstrCost()
1132 { ISD::FDIV, MVT::f32, { 7, 13, 1, 1 } }, // vdivss in getArithmeticInstrCost()
1419 { ISD::FDIV, MVT::f64, { 38, 38, 1, 1 } }, // (x87) in getArithmeticInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 455 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
456 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
1005 X86_INTRINSIC_DATA(avx512fp16_div_ph_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 115 ADD_BINARY_VVP_OP_COMPACT(FDIV)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 55 DAG_INSTRUCTION(FDiv, 2, 1, experimental_constrained_fdiv, FDIV)
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| H A D | VPIntrinsics.def | 324 HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 393 FDIV, enumerator
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| H A D | TargetLowering.h | 833 return N->getOpcode() == ISD::FDIV; in optimizeFMulOrFDivAsShiftAddBitcast()
2826 case ISD::FDIV: in isBinOp()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 550 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| H A D | SelectionDAGDumper.cpp | 271 case ISD::FDIV: return "fdiv"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 85 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1314 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
2424 case ISD::FDIV: in PromoteFloatResult()
2833 case ISD::FDIV: in SoftPromoteHalfResult()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP7.td | 307 def : InstRW<[P7_ScalarFPU_33C, P7_DISP_FP], (instrs FDIV, FDIV_rec)>;
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| H A D | PPCScheduleP8.td | 160 def : InstRW<[P8_FP_Scal_32C, P8_ISSUE_VSX], (instrs FDIV, FDIV_rec, XSDIVDP)>;
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| H A D | P10InstrResources.td | 56 FDIV,
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| H A D | P9InstrResources.td | 1133 FDIV
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
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| H A D | MipsSEISelLowering.cpp | 131 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
381 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
1855 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 672 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1906 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1931 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1983 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
3286 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 620 case ISD::FDIV: in getArithmeticInstrCost()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF1.td | 125 defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 553 // FDIV,FSQRT
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| H A D | AArch64SchedA57.td | 474 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 274 setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal); in LoongArchTargetLowering()
320 setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal); in LoongArchTargetLowering()
3008 return DAG.getNode(ISD::FDIV, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1861 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrArithmetic.td | 1094 defm FDIV : MxFBinaryOp<"div", 0b1100000, 0b1100100, 0b0100000>;
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