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Searched refs:FADD (Results 1 – 25 of 64) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def52 DAG_INSTRUCTION(FAdd, 2, 1, experimental_constrained_fadd, FADD)
101 // constrained FMA or FMUL + FADD intrinsics.
H A DVPIntrinsics.def315 HELPER_REGISTER_BINARY_FP_VP(fadd, VP_FADD, FAdd, FADD)
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1053 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd in getArithmeticInstrCost()
1111 { ISD::FADD, MVT::f64, { 1, 4, 1, 1 } }, // vaddsd in getArithmeticInstrCost()
1416 { ISD::FADD, MVT::f64, { 2, 3, 1, 1 } }, // (x87) in getArithmeticInstrCost()
1444 case ISD::FADD: in getArithmeticInstrCost()
5053 { ISD::FADD, MVT::v2f64, 3 }, in getArithmeticReductionCost()
5058 { ISD::FADD, MVT::v2f64, 2 }, in getArithmeticReductionCost()
5059 { ISD::FADD, MVT::v2f32, 2 }, in getArithmeticReductionCost()
5060 { ISD::FADD, MVT::v4f32, 4 }, in getArithmeticReductionCost()
5074 { ISD::FADD, MVT::v4f64, 3 }, in getArithmeticReductionCost()
5075 { ISD::FADD, MVT::v4f32, 3 }, in getArithmeticReductionCost()
[all …]
H A DX86IntrinsicsInfo.h430 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
431 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
1004 X86_INTRINSIC_DATA(avx512fp16_add_ph_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td15 CheckOpcode<[FADD,
H A DP9InstrResources.td416 (instregex "FADD(S)?$"),
476 (instregex "FADD(S)?_rec$"),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def112 ADD_BINARY_VVP_OP_COMPACT(FADD) REGISTER_PACKED(VVP_FADD)
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h390 FADD, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp5182 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5198 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5201 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5219 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5222 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5225 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5228 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
5231 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, in getLimitedPrecisionExp2()
5297 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, in expandLog()
6628 SDValue Add = DAG.getNode(ISD::FADD, sdl, in visitIntrinsicCall()
[all …]
H A DLegalizeVectorOps.cpp351 case ISD::FADD: in LegalizeOp()
1672 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1693 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
H A DSelectionDAGBuilder.h540 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
H A DDAGCombiner.cpp2006 case ISD::FADD: return visitFADD(N); in visit()
16139 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1; in visitFMULForFMADistributiveCombine()
16251 return DAG.getNode(ISD::FADD, DL, VT, N1, N0); in visitFADD()
16289 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B); in visitFADD()
16321 if (N1CFP && N0.getOpcode() == ISD::FADD && in visitFADD()
16377 if (N0.getOpcode() == ISD::FADD) { in visitFADD()
16388 if (N1.getOpcode() == ISD::FADD) { in visitFADD()
16400 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && in visitFADD()
16512 N1.getOpcode() == ISD::FADD) { in visitFSUB()
16524 return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1); in visitFSUB()
[all …]
H A DLegalizeFloatTypes.cpp77 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
1306 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
1860 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, NewLo); in ExpandFloatRes_XINT_TO_FP()
2423 case ISD::FADD: in PromoteFloatResult()
2832 case ISD::FADD: in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp2753 Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt); in ExpandLegalINT_TO_FP()
2762 Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, DestVT)) in ExpandLegalINT_TO_FP()
2831 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); in ExpandLegalINT_TO_FP()
3677 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode()
3681 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags); in ExpandNode()
4618 case ISD::FADD: in ConvertNodeToLibcall()
5251 case ISD::FADD: in PromoteNode()
H A DSelectionDAGDumper.cpp265 case ISD::FADD: return "fadd"; in getOperationName()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp480 ISD::FADD, ISD::FCEIL, ISD::FCOS, in AMDGPUTargetLowering()
574 ISD::STORE, ISD::FADD, in AMDGPUTargetLowering()
601 case ISD::FADD: in fnegFoldsIntoOpcode()
2345 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2481 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2506 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2646 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2700 R = DAG.getNode(ISD::FADD, DL, VT, R, FMA1, Flags); in LowerFLOGCommon()
3297 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
4704 case ISD::FADD: { in performFNegCombine()
[all …]
H A DAMDGPUTargetTransformInfo.cpp592 if (OPC == ISD::FADD || OPC == ISD::FSUB) { in getArithmeticInstrCost()
607 case ISD::FADD: in getArithmeticInstrCost()
H A DSIISelLowering.cpp208 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV, in SITargetLowering()
814 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA}, in SITargetLowering()
886 ISD::FADD, in SITargetLowering()
5621 case ISD::FADD: in LowerOperation()
12351 case ISD::FADD: in isCanonicalized()
13109 case ISD::FADD: in performExtractVectorEltCombine()
14005 if (LHS.getOpcode() == ISD::FADD) { in performFAddCombine()
14017 if (RHS.getOpcode() == ISD::FADD) { in performFAddCombine()
14048 if (LHS.getOpcode() == ISD::FADD) { in performFSubCombine()
14062 if (RHS.getOpcode() == ISD::FADD) { in performFSubCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp968 ISD != ISD::FADD) in getArithmeticReductionCost()
1328 case ISD::FADD: in getArithmeticInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp437 case ISD::FADD: in NVPTXTargetLowering()
725 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, in NVPTXTargetLowering()
740 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering()
2570 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32()
2601 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64()
5137 if (User->getOpcode() != ISD::FADD) in PerformADDCombineWithOperands()
5663 case ISD::FADD: in PerformDAGCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td595 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FABD|FADD|FSUB)v2f32$")>;
622 def : InstRW<[FalkorWr_2VXVY_3cyc], (instregex "^(FABD|FADD(P)?|FSUB)(v2f64|v4f32)$")>;
1126 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(FADD|FSUB)(S|D)rr$")>;
H A DAArch64SchedA57.td446 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
H A DAArch64SchedKryoDetails.td639 (instregex "(FABD|FADD|FSUB|FADDP)(v4f32|v2f64)")>;
669 (instregex "(FADD|FSUB)(D|S)rr")>;
675 (instregex "(FADD|FSUB|FADDP)v2f32")>;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td34 defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td123 defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;

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