| /freebsd-14.2/sys/contrib/device-tree/Bindings/phy/ |
| H A D | samsung-phy.txt | 1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY 30 Samsung Exynos SoC series Display Port PHY 41 Samsung S5P/Exynos SoC series USB PHY 66 meaning is compatible dependent. For the currently supported SoCs (Exynos 4210 67 and Exynos 4212) it is as follows: 74 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch 79 For Exynos 4412 (compatible with Exynos 4212): 195 Samsung Exynos SoC series PCIe PHY controller
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | samsung,exynos-bus.yaml | 7 title: Samsung Exynos SoC Bus and Interconnect 14 The Samsung Exynos SoC has many buses for data transfer between DRAM and 15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses. 16 Generally, each bus of Exynos SoC includes a source clock and a power line, 22 The Exynos SoC includes the various sub-blocks which have the each AXI bus. 41 There are a little different composition among Exynos SoC because each Exynos 44 able to support the bus frequency for all Exynos SoCs. 47 to Exynos SoC::
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | samsung,pinctrl-gpio-bank.yaml | 7 title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank 15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 18 GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
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| H A D | samsung,pinctrl-wakeup-interrupt.yaml | 7 title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller 15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 18 External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
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| H A D | samsung,pinctrl-pins-cfg.yaml | 7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration 15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin 18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | exynos-bus.txt | 1 * Generic Exynos Bus frequency device 3 The Samsung Exynos SoC has many buses for data transfer between DRAM 4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture 5 for buses. Generally, each bus of Exynos SoC includes a source clock 11 The Exynos SoC includes the various sub-blocks which have the each AXI bus. 30 There are a little different composition among Exynos SoC because each Exynos 33 is able to support the bus frequency for all Exynos SoCs. 67 Detailed correlation between sub-blocks and power line according to Exynos SoC:
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) 13 Samsung's Exynos architecture contains System MMUs that enables scattered 29 MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/power/ |
| H A D | pd-samsung.yaml | 7 title: Samsung Exynos SoC Power Domains 13 Exynos processors include support for multiple power domains which are used
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/usb/ |
| H A D | exynos-usb.txt | 1 Samsung Exynos SoC USB controller 3 The USB devices interface with USB controllers on Exynos SOCs. 93 The dwc3 core should be added as subnode to Exynos dwc3 glue.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/media/ |
| H A D | samsung,exynos5250-gsc.yaml | 7 title: Samsung Exynos SoC G-Scaler 15 G-Scaler is used for scaling and color space conversion on Samsung Exynos
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| H A D | exynos-jpeg-codec.txt | 1 Samsung S5P/Exynos SoC series JPEG codec
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/devfreq/event/ |
| H A D | samsung,exynos-ppmu.yaml | 7 title: Samsung Exynos SoC PPMU (Platform Performance Monitoring Unit) 14 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for 19 Exynos PPMU driver uses the devfreq-event class to provide event data to
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| H A D | exynos-ppmu.txt | 2 * Samsung Exynos PPMU (Platform Performance Monitoring Unit) device 4 The Samsung Exynos SoC has PPMU (Platform Performance Monitoring Unit) for 9 The Exynos PPMU driver uses the devfreq-event class to provide event data
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/display/exynos/ |
| H A D | exynos5433-decon.txt | 1 Device-Tree bindings for Samsung Exynos SoC display controller (DECON) 4 Exynos series of SoCs which transfers the image data from a video memory
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| H A D | exynos_hdmi.txt | 21 Required properties for Exynos 4210, 4212, 5420 and 5433: 36 Required properties for Exynos 5433:
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/display/samsung/ |
| H A D | samsung,exynos-mixer.yaml | 7 title: Samsung Exynos SoC Mixer 16 Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
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| H A D | samsung,exynos-hdmi-ddc.yaml | 7 title: Samsung Exynos SoC HDMI DDC
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredExynos.td | 10 // AArch64 Exynos processors. 25 // Exynos predicates.
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| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | exynos-syscon-restart.dtsi | 3 * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
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| H A D | exynos-mfc-reserved-memory.dtsi | 3 * Samsung's Exynos SoC MFC (Video Codec) reserved memory common definition.
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/rng/ |
| H A D | samsung,exynos5250-trng.txt | 1 Exynos True Random Number Generator
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| H A D | samsung,exynos5250-trng.yaml | 7 title: Samsung Exynos SoC True Random Number Generator
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/arm/samsung/ |
| H A D | samsung-boards.yaml | 7 title: Samsung Exynos and S5P SoC based boards 217 - description: Exynos Auto v9 based boards 220 - samsung,exynosautov9-sadk # Samsung Exynos Auto v9 SADK
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| H A D | samsung-secure-firmware.yaml | 7 title: Samsung Exynos Secure Firmware
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/clock/ |
| H A D | clk-exynos-audss.txt | 4 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock 5 binding described here is applicable to all SoCs in Exynos family.
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