| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APFixedPoint.h | 215 APSInt ExtVal =
218 return -((-ExtVal).relativeShl(getLsbWeight()));
219 return ExtVal.relativeShl(getLsbWeight());
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 625 int64_t ExtVal = IsBool ? CI->getZExtValue() : CI->getSExtValue(); in lowerAsmOperandForConstraint() local
626 Ops.push_back(MachineOperand::CreateImm(ExtVal)); in lowerAsmOperandForConstraint()
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| H A D | LegalizerHelper.cpp | 3510 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); in lowerStore() local
3514 auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt); in lowerStore()
3527 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); in lowerStore()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.h | 77 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | WebAssemblyISelLowering.cpp | 822 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
823 EVT ExtT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
824 EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0); in isVectorLoadExtDesirable()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 2450 ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0)); in optimizeCallInst() local
2451 if (!ExtVal || !ExtVal->hasOneUse() || in optimizeCallInst()
2452 ExtVal->getParent() == CI->getParent()) in optimizeCallInst()
2455 ExtVal->moveBefore(CI); in optimizeCallInst()
2458 InsertedInsts.insert(ExtVal); in optimizeCallInst()
4553 Value *ExtVal = SExt; in promoteOperandForTruncAndAnyExt() local
4563 ExtVal = ZExt; in promoteOperandForTruncAndAnyExt()
4576 Instruction *ExtInst = dyn_cast<Instruction>(ExtVal); in promoteOperandForTruncAndAnyExt()
4583 return ExtVal; in promoteOperandForTruncAndAnyExt()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 470 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | ARMISelLowering.cpp | 19398 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
19399 EVT VT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
19404 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal.getOperand(0))) { in isVectorLoadExtDesirable()
19416 if (ExtVal->use_empty() || in isVectorLoadExtDesirable()
19417 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode())) in isVectorLoadExtDesirable()
19420 SDNode *U = *ExtVal->use_begin(); in isVectorLoadExtDesirable()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2334 SDValue ExtVal = CurDAG->getConstant(Offset, DL, VT); in matchIndexRecursively() local
2335 SDValue ExtAdd = CurDAG->getNode(ISD::ADD, DL, VT, ExtSrc, ExtVal); in matchIndexRecursively()
2337 insertDAGNode(*CurDAG, N, ExtVal); in matchIndexRecursively()
2384 SDValue ExtVal = CurDAG->getConstant(Offset, DL, VT); in matchIndexRecursively() local
2385 SDValue ExtAdd = CurDAG->getNode(SrcOpc, DL, VT, ExtSrc, ExtVal); in matchIndexRecursively()
2387 insertDAGNode(*CurDAG, N, ExtVal); in matchIndexRecursively()
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| H A D | X86ISelLowering.cpp | 33795 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
33796 if (isa<MaskedLoadSDNode>(ExtVal.getOperand(0))) in isVectorLoadExtDesirable()
33799 EVT SrcVT = ExtVal.getOperand(0).getValueType(); in isVectorLoadExtDesirable()
57045 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue() in LowerAsmOperandForConstraint() local
57047 Result = DAG.getTargetConstant(ExtVal, SDLoc(Op), MVT::i64); in LowerAsmOperandForConstraint()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1255 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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| H A D | AArch64ISelLowering.cpp | 5527 bool AArch64TargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { in isVectorLoadExtDesirable()
5528 EVT ExtVT = ExtVal.getValueType(); in isVectorLoadExtDesirable()
5537 if (auto *Ld = dyn_cast<MaskedLoadSDNode>(ExtVal->getOperand(0))) { in isVectorLoadExtDesirable()
17716 uint64_t ExtVal = C->getZExtValue(); in performSVEAndCombine() local
17718 auto MaskAndTypeMatch = [ExtVal](EVT VT) -> bool { in performSVEAndCombine()
17719 return ((ExtVal == 0xFF && VT == MVT::i8) || in performSVEAndCombine()
17720 (ExtVal == 0xFFFF && VT == MVT::i16) || in performSVEAndCombine()
17721 (ExtVal == 0xFFFFFFFF && VT == MVT::i32)); in performSVEAndCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2984 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector() local
2987 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
2988 Ops.push_back(ExtVal); in LowerSTOREVector()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3088 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } in isVectorLoadExtDesirable() argument
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2154 SDValue ExtVal = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, in ExtendToInt64() local
2157 return ExtVal; in ExtendToInt64()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 5498 int64_t ExtVal = in LowerAsmOperandForConstraint() local
5501 DAG.getTargetConstant(Offset + ExtVal, SDLoc(C), MVT::i64)); in LowerAsmOperandForConstraint()
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| H A D | DAGCombiner.cpp | 14704 SDValue ExtVal = N0.getOperand(1); in visitTRUNCATE() local
14705 EVT ExtVT = cast<VTSDNode>(ExtVal)->getVT(); in visitTRUNCATE()
14708 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, TrX, ExtVal); in visitTRUNCATE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6831 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT() local
6835 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
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