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Searched refs:ExtTy (Results 1 – 25 of 28) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp112 IntegerType *ExtTy = nullptr; member in __anona30667b30111::IRPromoter
131 ExtTy = IntegerType::get(Ctx, PromotedWidth); in IRPromoter()
438 assert(V->getType() != ExtTy && "zext already extends to i32"); in ExtendSources()
444 Value *ZExt = Builder.CreateZExt(V, ExtTy); in ExtendSources()
487 if ((Op->getType() == ExtTy) || !isa<IntegerType>(Op->getType())) in PromoteTree()
504 I->setOperand(i, ConstantInt::get(ExtTy, 0)); in PromoteTree()
509 I->mutateType(ExtTy); in PromoteTree()
594 if (ZExt->getDestTy() != ExtTy) in Cleanup()
609 assert(Trunc->getOperand(0)->getType() == ExtTy && in Cleanup()
638 if (SrcTy != ExtTy) in ConvertTruncs()
[all …]
H A DCodeGenPrepare.cpp4284 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in addPromotedInst() local
4289 if (It->second.getInt() == ExtTy) in addPromotedInst()
4295 ExtTy = BothExtension; in addPromotedInst()
4306 ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; in getOrigType() local
4308 if (It != PromotedInsts.end() && It->second.getInt() == ExtTy) in getOrigType()
4518 Type *ExtTy = Ext->getType(); in getAction() local
5919 Type *ExtTy = FirstUser->getType(); in hasSameExtUse() local
5926 if (CurTy == ExtTy) in hasSameExtUse()
5945 if (ExtTy->getScalarType()->getIntegerBitWidth() > in hasSameExtUse()
5948 LargeTy = ExtTy; in hasSameExtUse()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h2101 Type *ExtTy = RetTy->getWithNewBitWidth(ExtSize); in getTypeBasedIntrinsicInstrCost() local
2110 thisT()->getArithmeticInstrCost(Instruction::Mul, ExtTy, CostKind); in getTypeBasedIntrinsicInstrCost()
2167 Type *ExtTy = MulTy->getWithNewBitWidth(ExtSize); in getTypeBasedIntrinsicInstrCost() local
2179 Cost += thisT()->getArithmeticInstrCost(Instruction::LShr, ExtTy, in getTypeBasedIntrinsicInstrCost()
2530 VectorType *ExtTy = VectorType::get(ResTy, Ty); in getExtendedReductionCost() local
2532 thisT()->getArithmeticReductionCost(Opcode, ExtTy, FMF, CostKind); in getExtendedReductionCost()
2534 IsUnsigned ? Instruction::ZExt : Instruction::SExt, ExtTy, Ty, in getExtendedReductionCost()
2546 VectorType *ExtTy = VectorType::get(ResTy, Ty); in getMulAccReductionCost() local
2548 Instruction::Add, ExtTy, std::nullopt, CostKind); in getMulAccReductionCost()
2550 IsUnsigned ? Instruction::ZExt : Instruction::SExt, ExtTy, Ty, in getMulAccReductionCost()
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H A DSelectionDAGNodes.h569 uint16_t ExtTy : 2; // enum ISD::LoadExtType
2390 LoadSDNodeBits.ExtTy = ETy;
2399 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2529 LoadSDNodeBits.ExtTy = ETy;
2534 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2558 LoadSDNodeBits.ExtTy = ETy;
2563 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2701 LoadSDNodeBits.ExtTy = ETy;
2706 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2889 LoadSDNodeBits.ExtTy = ETy;
[all …]
H A DSelectionDAG.h1570 ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy);
H A DTargetLowering.h1728 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h131 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1480 LLT MidTy, ExtTy; in legalizeIntrinsic() local
1483 ExtTy = LLT::scalar(32); in legalizeIntrinsic()
1486 ExtTy = LLT::scalar(64); in legalizeIntrinsic()
1493 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DGlobalISelEmitter.cpp1520 const TypeSetByHwMode &ExtTy = Dst->getExtType(I); in importExplicitDefRenderers() local
1521 if (!ExtTy.isMachineValueType()) in importExplicitDefRenderers()
1524 auto OpTy = MVTToLLT(ExtTy.getMachineValueType().SimpleTy); in importExplicitDefRenderers()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2429 MVT ExtTy = MVT::getVectorVT(MVT::i16, Ty.getVectorNumElements()); in LowerVECTOR_SHIFT() local
2430 SDValue ExtV = Opc == HexagonISD::VASR ? DAG.getSExtOrTrunc(V, dl, ExtTy) in LowerVECTOR_SHIFT()
2431 : DAG.getZExtOrTrunc(V, dl, ExtTy); in LowerVECTOR_SHIFT()
2432 SDValue ExtS = DAG.getNode(Opc, dl, ExtTy, {ExtV, A}); in LowerVECTOR_SHIFT()
3815 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth() argument
3817 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
H A DHexagonISelLowering.h342 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DHexagonISelLoweringHVX.cpp890 MVT ExtTy = ty(ExtVec); in buildHvxVectorReg() local
891 unsigned ExtLen = ExtTy.getVectorNumElements(); in buildHvxVectorReg()
916 SDValue S = DAG.getVectorShuffle(ExtTy, dl, ExtVec, in buildHvxVectorReg()
917 DAG.getUNDEF(ExtTy), Mask); in buildHvxVectorReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp343 LLT ExtTy = getLLTForType(*RetInfo.Ty, DL); in lowerReturnVal() local
344 Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0); in lowerReturnVal()
H A DAMDGPUISelLowering.cpp771 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
774 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h653 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DAArch64ISelLowering.cpp4456 const EVT &ExtTy, in addRequiredExtensionForVectorMULL() argument
4461 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
14662 ISD::LoadExtType ExtTy, in shouldReduceLoadWidth() argument
14665 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
14670 if (ExtTy != ISD::NON_EXTLOAD) in shouldReduceLoadWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1417 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
H A DX86InstrSSE.td5043 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy,
5067 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5075 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5077 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5080 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5082 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5085 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5122 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5143 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5147 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
[all …]
H A DX86InstrAVX512.td9903 SDNode OpNode, SDNode InVecNode, string ExtTy,
9905 PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9923 SDNode OpNode, SDNode InVecNode, string ExtTy,
9925 PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
9943 SDNode InVecNode, string ExtTy,
9963 SDNode OpNode, SDNode InVecNode, string ExtTy,
9965 PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
9983 SDNode OpNode, SDNode InVecNode, string ExtTy,
9985 PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
10003 SDNode OpNode, SDNode InVecNode, string ExtTy,
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Analysis/
H A DScalarEvolution.cpp3457 IntegerType *ExtTy = in getUDivExpr() local
3466 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3467 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3468 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3480 getZeroExtendExpr(AR, ExtTy) == in getUDivExpr()
3481 getAddRecExpr(getZeroExtendExpr(AR->getStart(), ExtTy), in getUDivExpr()
3482 getZeroExtendExpr(Step, ExtTy), in getUDivExpr()
3510 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
3511 if (getZeroExtendExpr(M, ExtTy) == getMulExpr(Operands)) in getUDivExpr()
3542 Operands.push_back(getZeroExtendExpr(Op, ExtTy)); in getUDivExpr()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp2470 Type *ExtTy = Type::getInt32Ty(C); in UpgradeIntrinsicCall() local
2472 ExtTy = Type::getInt64Ty(C); in UpgradeIntrinsicCall()
2474 ExtTy->getPrimitiveSizeInBits(); in UpgradeIntrinsicCall()
2475 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); in UpgradeIntrinsicCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp1390 Type *ExtTy = VectorType::get(IntptrTy, cast<VectorType>(Ty)); in getInterestingMemoryOperands() local
1391 Value *ExtMask = IB.CreateZExt(Mask, ExtTy); in getInterestingMemoryOperands()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2236 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateReg() argument
2244 Op->Reg.ShiftExtend.Type = ExtTy; in CreateReg()
2255 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateVectorReg() argument
2262 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp9346 ISD::LoadExtType ExtTy, bool isExpanding) { in getMaskedLoad() argument
9357 dl.getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO)); in getMaskedLoad()
9366 AM, ExtTy, isExpanding, MemVT, MMO); in getMaskedLoad()
9440 ISD::LoadExtType ExtTy) { in getMaskedGather() argument
9447 dl.getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy)); in getMaskedGather()
9457 VTs, MemVT, MMO, IndexType, ExtTy); in getMaskedGather()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp3939 LLT ExtTy = MRI.getType(DstReg); in applyExtendThroughPhis() local
3960 auto NewExt = Builder.buildExtOrTrunc(ExtMI->getOpcode(), ExtTy, SrcReg); in applyExtendThroughPhis()

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