Home
last modified time | relevance | path

Searched refs:ExtReg (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp62 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
70 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
74 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp111 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
123 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp66 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
74 LLT Ty = MRI.getType(ExtReg); in assignValueToReg()
81 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
88 {MRI.getType(ExtReg)}) in assignValueToReg()
89 .addReg(ExtReg); in assignValueToReg()
90 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
93 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
236 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
237 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
H A DAMDGPUInstructionSelector.cpp2505 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2510 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2517 .addReg(ExtReg) in selectG_SZA_EXT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp54 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
55 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp120 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
121 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
128 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
131 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp223 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
254 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
255 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp96 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
97 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
106 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
107 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp931 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
934 SrcReg1 = ExtReg; in PPCEmitCmp()
937 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
940 SrcReg2 = ExtReg; in PPCEmitCmp()
H A DPPCISelLowering.cpp11931 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
11933 ExtReg).addReg(dest); in EmitAtomicBinary()
11934 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ExtReg).addReg(incr); in EmitAtomicBinary()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7255 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
7541 Register ExtReg; in selectArithExtendedRegister() local
7568 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7574 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7581 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
7590 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
7592 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
7615 Register ExtReg = Extract->MI->getOperand(2).getReg(); in selectExtractHigh() local
7616 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}}; in selectExtractHigh()
7625 Register ExtReg = Extract->MI->getOperand(1).getReg(); in selectExtractHigh() local
[all …]
H A DAArch64CallLowering.cpp289 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
290 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
H A DAArch64LegalizerInfo.cpp1493 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic() local
1498 MIB.buildTrunc(DstReg, ExtReg); in legalizeIntrinsic()
1500 MIB.buildCopy(DstReg, ExtReg); in legalizeIntrinsic()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1096 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1098 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1102 Reg = ExtReg; in X86SelectCallAddress()