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Searched refs:ExtOpc (Results 1 – 18 of 18) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp870 switch (ExtOpc) { in getRegOffOpcode()
883 switch (ExtOpc) { in getRegOffOpcode()
957 return ExtOpc; in getRegOffOpcode()
967 switch (ExtOpc) { in getDirectRegReplacement()
1608 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExact() local
1635 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) { in replaceInstrExact()
1726 unsigned ExtOpc = MI.getOpcode(); in replaceInstrExpr() local
1728 if (ExtOpc == Hexagon::A2_tfrsi) { in replaceInstrExpr()
1773 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) { in replaceInstrExpr()
1791 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii || in replaceInstrExpr()
[all …]
H A DHexagonBitSimplify.cpp2542 unsigned ExtOpc = 0; in simplifyExtractLow() local
2545 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2547 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2549 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2551 if (ExtOpc == 0) { in simplifyExtractLow()
2552 ExtOpc = in simplifyExtractLow()
2564 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2568 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2580 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2582 switch (ExtOpc) { in simplifyExtractLow()
H A DHexagonISelLoweringHVX.cpp1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth() local
1586 return DAG.getNode(ExtOpc, dl, ResTy, VecV); in resizeToWidth()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp422 auto ExtOpc = ExtMI->getOpcode(); in matchExtUaddvToUaddlv() local
424 if (ExtOpc == TargetOpcode::G_ZEXT) in matchExtUaddvToUaddlv()
426 else if (ExtOpc == TargetOpcode::G_SEXT) in matchExtUaddvToUaddlv()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp526 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
529 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
530 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
540 Opcode = ExtOpc; in buildExtOrTrunc()
H A DLegalizerHelper.cpp2396 unsigned ExtOpc = MI.getOpcode() == TargetOpcode::G_CTTZ || in widenScalar() local
2400 auto MIBSrc = MIRBuilder.buildInstr(ExtOpc, {WideTy}, {SrcReg}); in widenScalar()
2677 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2679 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2680 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2683 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
H A DCombinerHelper.cpp530 static unsigned getExtLoadOpcForExtend(unsigned ExtOpc) { in getExtLoadOpcForExtend() argument
532 switch (ExtOpc) { in getExtLoadOpcForExtend()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp3305 Instruction::CastOps ExtOpc = Instruction::CastOps::CastOpsEnd; in visitCallInst() local
3307 ExtOpc = cast<CastInst>(Arg)->getOpcode(); in visitCallInst()
3309 (ExtOpc == Instruction::CastOps::ZExt)) in visitCallInst()
3313 Res = Builder.CreateCast(ExtOpc, Res, II->getType()); in visitCallInst()
H A DInstCombineCompares.cpp7177 unsigned ExtOpc = ExtI->getOpcode(); in visitICmpInst() local
7179 if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) || in visitICmpInst()
7180 (ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) { in visitICmpInst()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1900 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1903 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1905 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1917 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1669 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
1678 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
1683 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
1684 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h780 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4015 unsigned ExtOpc = in lowerScalarSplat() local
4017 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
4082 unsigned ExtOpc = in lowerScalarInsert() local
4084 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarInsert()
8267 unsigned ExtOpc = in lowerVectorIntrinsicScalars() local
8269 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
11637 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
11639 ExtOpc = N->getOpcode() == ISD::SDIV ? ISD::SIGN_EXTEND in ReplaceNodeResults()
11642 Results.push_back(customLegalizeToWOp(N, DAG, ExtOpc)); in ReplaceNodeResults()
13085 unsigned ExtOpc = *SExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL; in getOrCreateExtendedOp() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1543 unsigned ExtOpc = in PromoteOperand() local
1545 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
7069 unsigned ExtOpc = N0.getOpcode(); in visitAND() local
7072 (ExtOpc != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0Op0, VT)) && in visitAND()
12807 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
12820 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
12822 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
13143 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
13157 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI); in tryToFoldExtOfLoad()
13167 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc); in tryToFoldExtOfLoad()
[all …]
H A DLegalizeIntegerTypes.cpp5699 unsigned ExtOpc = ISD::ANY_EXTEND; in PromoteIntRes_BUILD_VECTOR() local
5704 ExtOpc = NOutExtOpc; in PromoteIntRes_BUILD_VECTOR()
5705 Op = DAG.getNode(ExtOpc, dl, NOutVTElem, Op); in PromoteIntRes_BUILD_VECTOR()
H A DTargetLowering.cpp5496 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
5499 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp20031 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
20032 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
24259 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
24262 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
29392 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
46967 unsigned ExtOpc = LHS.getOpcode(); in combineShiftToPMULH() local
46968 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) || in combineShiftToPMULH()
46969 RHS.getOpcode() != ExtOpc) in combineShiftToPMULH()
46985 return DAG.getNode(ExtOpc, DL, VT, Mulh); in combineShiftToPMULH()
47406 if (N0.getOpcode() == ExtOpc && in combineVectorPack()
[all …]
H A DX86TargetTransformInfo.cpp3044 unsigned ExtOpc = in getCastInstrCost() local
3050 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()