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Searched refs:Ext2 (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DMsgPack.def95 HANDLE_MP_FIX_LEN(0x02, Ext2)
/freebsd-14.2/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DMsgPackWriter.cpp182 case FixLen::Ext2: in writeExt()
H A DMsgPackReader.cpp126 return createExt(Obj, FixLen::Ext2); in read()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14907 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
14914 !match(Ext2, m_ZExtOrSExt(m_Value())) || in areExtractExts()
14916 !areExtDoubled(cast<Instruction>(Ext2))) in areExtractExts()
15120 auto Ext2 = cast<Instruction>(I->getOperand(1)); in shouldSinkOperands() local
15121 if (areExtractShuffleVectors(Ext1->getOperand(0), Ext2->getOperand(0))) { in shouldSinkOperands()
15123 Ops.push_back(&Ext2->getOperandUse(0)); in shouldSinkOperands()
20328 const SDValue Ext2 = in performSignExtendSetCCCombine() local
20332 SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, in performSignExtendSetCCCombine()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14874 SDValue Ext2 = N->getOperand(1).getOperand(0); in DAGCombineBuildVector() local
14876 Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in DAGCombineBuildVector()
14880 ConstantSDNode *Ext2Op = dyn_cast<ConstantSDNode>(Ext2.getOperand(1)); in DAGCombineBuildVector()
14884 Ext1.getOperand(0) != Ext2.getOperand(0)) in DAGCombineBuildVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp10318 SDValue Ext2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10323 SDValue Res1 = DAG.getNode(BaseOpcode, dl, EltVT, Ext2, Ext3, Op->getFlags()); in LowerVecReduce()
19244 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
19251 !match(Ext2, m_ZExtOrSExt(m_Value())) || in areExtractExts()
19253 !areExtDoubled(cast<Instruction>(Ext2))) in areExtractExts()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp12713 SDValue Ext2 = DAG.getNode(Opcode, DL, VT, Op2); in tryToFoldExtendSelectLoad() local
12714 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); in tryToFoldExtendSelectLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp43895 SDValue Ext2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in scalarizeExtEltFP() local
43897 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
55629 SDValue Ext2 = extractSubVector(InVec.getOperand(2), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
55630 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()