| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 367 return Ext0; in getShuffleExtract()
376 return Ext0; in getShuffleExtract()
379 return Index0 > Index1 ? Ext0 : Ext1; in getShuffleExtract()
397 Type *ScalarTy = Ext0->getType(); in isExtractExtractCheap()
444 bool HasUseTax = Ext0 == Ext1 ? !Ext0->hasNUses(2) in isExtractExtractCheap()
585 auto *Ext0 = cast<ExtractElementInst>(I0); in foldExtractExtract() local
602 if (ExtractToChange == Ext0) in foldExtractExtract()
603 Ext0 = NewExtract; in foldExtractExtract()
609 foldExtExtCmp(Ext0, Ext1, I); in foldExtractExtract()
611 foldExtExtBinop(Ext0, Ext1, I); in foldExtractExtract()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10314 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10326 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10330 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
13358 SDValue Ext0 = Mul.getOperand(0); in PerformVQDMULHCombine() local
13360 if (Ext0.getOpcode() != ISD::SIGN_EXTEND || in PerformVQDMULHCombine()
13363 EVT VecVT = Ext0.getOperand(0).getValueType(); in PerformVQDMULHCombine()
13381 DAG.getNode(ISD::ANY_EXTEND, DL, ExtVecVT, Ext0.getOperand(0)); in PerformVQDMULHCombine()
13398 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
17219 SDValue Ext0 = in PerformVECREDUCE_ADDCombine() local
17227 Ext0, Ext1); in PerformVECREDUCE_ADDCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 16711 SDValue Ext0 = Op0.getOperand(0); in performUADDVAddCombine() local
16713 if (Ext0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVAddCombine()
16715 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVAddCombine()
16722 if ((Ext0.getConstantOperandVal(1) != 0 || in performUADDVAddCombine()
16729 return DAG.getNode(Opcode, SDLoc(A), VT, Ext0.getOperand(0)); in performUADDVAddCombine()
16759 SDValue Ext0 = Op0.getOperand(0); in performUADDVZextCombine() local
16761 EVT ExtVT0 = Ext0.getValueType(); in performUADDVZextCombine()
19501 SDValue Ext0, Ext1; in performExtBinopLoadFold() local
19515 Ext0 = DAG.getNode(Other.getOpcode(), DL, VT, Extr0); in performExtBinopLoadFold()
19525 Ext0 = DAG.getVectorShuffle(VT, DL, SubL, SubH, LowMask); in performExtBinopLoadFold()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 2936 Instruction *Ext0, *Ext1; in foldICmpAddConstant() local
2939 m_Add(m_CombineAnd(m_Instruction(Ext0), m_ZExtOrSExt(m_Value(Op0))), in foldICmpAddConstant()
2949 Res += isa<ZExtInst>(Ext0) ? 1 : -1; in foldICmpAddConstant()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3654 auto Ext0 = B.buildFPExt(F32, Log, Flags); in legalizeFPow() local
3657 .addUse(Ext0.getReg(0)) in legalizeFPow()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41521 SDValue Ext0 = in SimplifyDemandedVectorEltsForTargetNode() local
41524 TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0, Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode()
43867 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
43871 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
43890 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in scalarizeExtEltFP() local
43897 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
55627 SDValue Ext0 = extractSubVector(InVec.getOperand(0), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
55630 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
55643 SDValue Ext0 = in combineEXTRACT_SUBVECTOR() local
55645 return DAG.getNode(InOpcode, DL, VT, Ext0); in combineEXTRACT_SUBVECTOR()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 13329 SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); in foldSextSetcc() local
13331 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
22016 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Index); in scalarizeExtractedBinop() local
22018 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
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