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Searched refs:EndGroup (Results 1 – 16 of 16) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp51 assert((SC->NumMicroOps != 2 || (SC->BeginGroup && !SC->EndGroup)) && in getNumDecoderSlots()
53 assert((SC->NumMicroOps < 3 || (SC->BeginGroup && SC->EndGroup)) && in getNumDecoderSlots()
196 if (SC->BeginGroup && SC->EndGroup) in dumpSU()
200 else if (SC->EndGroup) in dumpSU()
336 if (CurrGroupSize >= GroupLim || SC->EndGroup) in EmitInstruction()
355 if (SC->EndGroup) { in groupingCost()
H A DSystemZScheduleZ196.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
44 let EndGroup = 1;
49 let EndGroup = 1;
54 let EndGroup = 1;
95 let EndGroup = 1; }
136 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Cond)?Trap$")>;
204 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, EndGroup],
650 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
653 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1095 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZScheduleZEC12.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
44 let EndGroup = 1;
49 let EndGroup = 1;
54 let EndGroup = 1;
98 let EndGroup = 1; }
124 def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;
663 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
666 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1139 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
1140 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SSM$")>;
[all …]
H A DSystemZScheduleZ13.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
140 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
586 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
693 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
696 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1414 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZSchedule.td20 def EndGroup : SchedWrite;
H A DSystemZScheduleZ16.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
115 let EndGroup = 1; }
142 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
610 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
728 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
731 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1573 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZScheduleZ14.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
141 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
596 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
713 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
716 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1503 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZScheduleZ15.td39 def : WriteRes<EndGroup, []> { let EndGroup = 1; }
48 let EndGroup = 1;
53 let EndGroup = 1;
58 let EndGroup = 1;
114 let EndGroup = 1; }
141 def : InstRW<[WLat1, FXa, EndGroup], (instregex "BRCT(G)?$")>;
610 def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>;
728 def : InstRW<[WLat3, FXa, EndGroup], (instregex "IPM$")>;
731 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
1549 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
[all …]
H A DSystemZMachineScheduler.cpp255 bool AffectsGrouping = (SC->isValid() && (SC->BeginGroup || SC->EndGroup)); in releaseTopNode()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h527 bool EndGroup : 1; variable
585 void setEndGroup(bool newVal) { EndGroup = newVal; } in setEndGroup()
592 bool getEndGroup() const { return EndGroup; } in getEndGroup()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h127 uint16_t EndGroup : 1; member
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM85.td330 let ReleaseAtCycles = [2,2,1,1], EndGroup = 1 in {
703 let Latency = 4, EndGroup = 1 in {
716 let Latency = 3, EndGroup = 1 in {
725 let Latency = 2, EndGroup = 1 in {
735 let Latency = 1, EndGroup = 1 in {
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp90 return SC->EndGroup; in mustEndGroup()
/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1045 SCDesc.EndGroup = false; in GenSchedClassTables()
1146 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup"); in GenSchedClassTables()
1148 SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue"); in GenSchedClassTables()
1419 << ", " << ( MCDesc.EndGroup ? "true" : "false" ) in EmitSchedClassTables()
/freebsd-14.2/contrib/llvm-project/llvm/lib/MCA/
H A DInstrBuilder.cpp657 NewIS->setEndGroup(SCDesc.EndGroup); in createInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td268 bit EndGroup = false;