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Searched refs:ElemVT (Results 1 – 8 of 8) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h125 MVT getLegalVectorType(Packing P, MVT ElemVT);
216 EVT getVectorVT(EVT ElemVT, unsigned NumElems) const { in getVectorVT() argument
217 return EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems); in getVectorVT()
H A DVECustomDAG.cpp34 MVT getLegalVectorType(Packing P, MVT ElemVT) { in getLegalVectorType() argument
35 return MVT::getVectorVT(ElemVT, P == Packing::Normal ? StandardVectorWidth in getLegalVectorType()
H A DVEISelLowering.cpp341 MVT ElemVT = VT.getVectorElementType(); in initVPUActions() local
342 unsigned ElemBits = ElemVT.getScalarSizeInBits(); in initVPUActions()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp106 EVT ElemVT = NOutVT; in ExpandRes_BITCAST() local
107 EVT NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems); in ExpandRes_BITCAST()
111 unsigned NewSizeInBits = ElemVT.getSizeInBits() / 2; in ExpandRes_BITCAST()
116 ElemVT = EVT::getIntegerVT(*DAG.getContext(), NewSizeInBits); in ExpandRes_BITCAST()
117 NVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, NumElems); in ExpandRes_BITCAST()
125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
H A DLegalizeVectorTypes.cpp6792 EVT ElemVT = OrigVT.getVectorElementType(); in WidenVecOp_VECREDUCE() local
6797 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
6806 EVT SplatVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, in WidenVecOp_VECREDUCE()
6830 EVT ElemVT = OrigVT.getVectorElementType(); in WidenVecOp_VECREDUCE_SEQ() local
6835 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
6843 EVT SplatVT = EVT::getVectorVT(*DAG.getContext(), ElemVT, in WidenVecOp_VECREDUCE_SEQ()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h721 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3813 MVT ElemVT = VT.getVectorElementType(); in lowerBUILD_VECTOR() local
3814 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerBUILD_VECTOR()
3816 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerBUILD_VECTOR()
4677 MVT ElemVT = VT.getVectorElementType(); in lowerShuffleViaVRegSplitting() local
4678 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerShuffleViaVRegSplitting()
4708 MVT OneRegVT = MVT::getVectorVT(ElemVT, ElemsPerVReg); in lowerShuffleViaVRegSplitting()
7951 EVT ElemVT = VecVT.getVectorElementType(); in lowerINSERT_VECTOR_ELT() local
8164 EVT ElemVT = VecVT.getVectorElementType(); in lowerEXTRACT_VECTOR_ELT() local
8165 unsigned ElemsPerVReg = MinVLen / ElemVT.getFixedSizeInBits(); in lowerEXTRACT_VECTOR_ELT()
19783 EVT ElemVT = VT.getVectorElementType(); in allowsMisalignedMemoryAccesses() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14117 EVT ElemVT = VecVT.getVectorElementType(); in getVectorBitwiseReduce() local
14123 if (ElemVT == MVT::i1) { in getVectorBitwiseReduce()
14183 DAG.getConstant(Shift * ElemVT.getSizeInBits(), DL, MVT::i64); in getVectorBitwiseReduce()
14189 Result = DAG.getAnyExtOrTrunc(Scalar, DL, ElemVT); in getVectorBitwiseReduce()