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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 42) sorted by relevance

12

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp145 setOperationAction(ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
401 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
1621 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1629 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1704 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
[all …]
H A DSIISelLowering.cpp331 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
628 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
911 ISD::EXTRACT_VECTOR_ELT, in SITargetLowering()
5563 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5888 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
11802 case ISD::EXTRACT_VECTOR_ELT: { in calculateByteProvider()
12443 case ISD::EXTRACT_VECTOR_ELT: in isCanonicalized()
14142 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
14143 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
14161 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
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H A DAMDGPUISelDAGToDAG.cpp56 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in isExtractHiElt()
84 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in stripExtractLoElt()
739 if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
740 BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp281 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in ScalarizeVecRes_StrictFPOp()
364 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
379 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_FP_ROUND()
437 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
499 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
617 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
619 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
644 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Arg, in ScalarizeVecRes_IS_FPCLASS()
699 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
4653 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in WidenVecRes_StrictFP()
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H A DLegalizeTypesGeneric.cpp125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
237 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
241 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeFloatTypes.cpp69 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
267 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
1296 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
2396 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
2558 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2802 case ISD::EXTRACT_VECTOR_ELT: in SoftPromoteHalfResult()
2890 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftPromoteHalfRes_EXTRACT_VECTOR_ELT()
H A DLegalizeDAG.cpp1027 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
3379 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
3465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
3469 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
4211 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
4214 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
4940 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
5433 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
5468 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
5517 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
H A DLegalizeVectorOps.cpp1878 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollStrictFPOp()
1916 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1918 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
H A DDAGCombiner.cpp721 case ISD::EXTRACT_VECTOR_ELT: in getStoreSource()
7092 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
8757 case ISD::EXTRACT_VECTOR_ELT: { in calculateByteProvider()
14726 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
19935 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
21460 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in mergeEltWithShuffle()
21719 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
21742 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
22998 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
23420 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp79 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
715 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
720 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1785 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
2618 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
5624 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
5802 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, in PromoteIntRes_CONCAT_VECTORS()
5885 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
5951 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAG.cpp3832 case ISD::EXTRACT_VECTOR_ELT: { in computeKnownBits()
4688 case ISD::EXTRACT_VECTOR_ELT: { in ComputeNumSignBits()
5204 case ISD::EXTRACT_VECTOR_ELT: { in isKnownNeverNaN()
5453 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || in FoldBUILD_VECTOR()
5833 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
6825 case ISD::EXTRACT_VECTOR_ELT: in getNode()
6849 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
6908 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), in getNode()
7861 Value = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, TailValue, in getMemsetStores()
11938 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchBinOpReduction()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp488 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
497 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2bf16, Custom); in NVPTXTargetLowering()
508 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom); in NVPTXTargetLowering()
513 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom); in NVPTXTargetLowering()
2358 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2360 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2690 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2973 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
5605 DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, VA, in PerformVSELECTCombine()
5609 DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i8, VB, in PerformVSELECTCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h535 EXTRACT_VECTOR_ELT, enumerator
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp215 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1460 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1896 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1921 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1991 if (ExtractVector.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerConvertLow()
2066 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2073 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
2089 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp172 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
254 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
1027 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in ARMTargetLowering()
8789 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
15233 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformVMOVrhCombine()
15512 if (Ext.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in PerformExtractEltToVMOVRRD()
15530 return V->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformExtractEltToVMOVRRD()
15551 ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformExtractEltToVMOVRRD()
17865 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp416 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
709 ISD::EXTRACT_VECTOR_ELT, in SystemZTargetLowering()
5642 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
6197 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
6560 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
6573 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
7125 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT, in combineEXTRACT_VECTOR_ELT()
7185 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
7192 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
7249 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_EXTEND()
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H A DSystemZISelDAGToDAG.cpp722 if (Index.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in selectBDVAddr12Only()
1256 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in tryScatter()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2435 ISD::EXTRACT_VECTOR_ELT, in X86TargetLowering()
6727 case ISD::EXTRACT_VECTOR_ELT: in findEltLoadSrc()
7425 if (Opc != ISD::EXTRACT_VECTOR_ELT) { in buildFromShuffleMostly()
8594 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTORAsVariablePermute()
17848 case ISD::EXTRACT_VECTOR_ELT: in getExtractedDemandedElts()
21567 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
22069 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchScalarReduction()
22333 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in MatchVectorAllEqualTest()
33107 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
48764 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineAnd()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp694 if (ISD == ISD::EXTRACT_VECTOR_ELT && in getVectorInstrCost()
748 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4476 if (OpNode->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in getConstantLaneNumOfExtractHalfOperand()
6212 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
10954 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in ReconstructShuffleWithRuntimeMask()
13033 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
18450 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in tryCombineFixedPointConvert()
18691 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performAddUADDVCombine()
19265 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in performAddSubIntoVectorOp()
19268 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT && in performAddSubIntoVectorOp()
19273 if (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in performAddSubIntoVectorOp()
23978 case ISD::EXTRACT_VECTOR_ELT: in PerformDAGCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp235 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
869 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1689 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1691 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
2017 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, ValAsVec, Idx); in LowerHvxBitcast()
3209 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp319 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
336 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1919 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
3122 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in lowerEXTRACT_VECTOR_ELT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp292 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
295 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
973 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
976 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
1632 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); in addMSAIntType()
374 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
457 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
1772 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1790 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1278 ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
3306 if (SplatVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchSplatAsGather()
4044 if (Scalar.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in lowerScalarInsert()
6000 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
11830 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
12123 if (RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in combineBinOpOfExtractToReduceTree()
12126 if (RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in combineBinOpOfExtractToReduceTree()
12144 if (LHS.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineBinOpOfExtractToReduceTree()
12216 return V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineBinOpToReduce()
15868 Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformDAGCombine()
[all …]

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