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Searched refs:ESP (Results 1 – 25 of 46) sorted by relevance

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/freebsd-14.2/sbin/setkey/
H A Dsample.cf32 # security protocol (AH or ESP) identifier. You must take care of these
35 # ESP transport mode is recommended for TCP port number 110 between
40 # ============ ESP ============
100 # AH transport mode followed by ESP tunnel mode is required between
106 # | ======= ESP ===== |
133 # ESP tunnel mode is required between Host-A and Gateway-A.
135 # for ESP is hmac-sha2-256.
136 # ESP transport mode is recommended between Host-A and Host-B.
138 # for ESP is hmac-sha2-512.
140 # ================== ESP =================
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/freebsd-14.2/release/tools/
H A Dvmimage.subr274 ESP=yes
281 ESP=yes
287 ESP=no
302 if [ ${ESP} = "yes" ]; then
327 if [ ${ESP} = "yes" ]; then
/freebsd-14.2/contrib/file/magic/Magdir/
H A Dfirmware71 # ESP-IDF partition table entry
75 >2 ubyte <2 ESP-IDF partition table entry
112 # ESP-IDF application image
118 >32 ulelong 0xABCD5432 ESP-IDF application image
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Support/Solaris/sys/
H A Dregset.h28 #undef ESP
/freebsd-14.2/sys/cddl/dev/dtrace/x86/
H A Dregset.h106 #define ESP 6 macro
/freebsd-14.2/sys/i386/i386/
H A Dbpf_jit_machdep.c207 MOVrd(ESP, EBP); in bpf_jit_compile()
210 SUBib(BPF_MEMWORDS * sizeof(uint32_t), ESP); in bpf_jit_compile()
309 MOVrd(ESP, ECX); in bpf_jit_compile()
318 MOVrd(ESP, ECX); in bpf_jit_compile()
H A Dbpf_jit_machdep.h44 #define ESP 4 macro
/freebsd-14.2/share/examples/IPv6/
H A DUSAGE397 From HOST B to HOST A, new AH and new ESP are combined.
400 AH"/"ESP"/"new ESP". Please refer to the "setkey" man page to know
402 and new-DES-expIV with 8 byte IV for new ESP.
436 PROTO=ESP
437 ALG=new-DES-expIV(new ESP)
469 the "ping" command has the -P option with parameter to enable AH and/or ESP.
477 to be AH transport mode inner ESP tunnel mode like below.
482 | ======= ESP ======= |
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td242 def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>;
288 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
575 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D,
630 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>;
650 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
676 // GR32_NOSP - GR32 registers except ESP.
677 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
683 // ESP.
691 // GR32_NOREX2_NOSP - GR32_NOREX2 registers except ESP.
693 (sub GR32_NOREX2, ESP)>;
[all …]
H A DX86InstrControl.td205 // All calls clobber the non-callee saved registers. ESP is marked as
209 let Uses = [ESP, SSP] in {
277 isCodeGenOnly = 1, Uses = [ESP, SSP] in {
300 let Uses = [ESP, EFLAGS, SSP] in {
H A DX86InstrMisc.td41 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
59 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
116 SchedRW = [WriteRMW], Defs = [ESP] in {
117 let Uses = [ESP] in
130 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
141 let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
148 let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
217 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
224 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
H A DX86IndirectThunks.cpp253 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk()
H A DX86FixupLEAs.cpp570 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
658 if (p.isReg() && p.getReg() != X86::ESP) { in processInstruction()
662 if (q.isReg() && q.getReg() != X86::ESP) { in processInstruction()
H A DX86RegisterInfo.cpp68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
999 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
H A DX86FrameLowering.cpp1168 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP; in emitStackProbeCall()
2063 .addReg(X86::ESP); in emitPrologue()
2322 Register StackReg = X86::ESP; in emitEpilogue()
2390 TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true); in emitEpilogue()
3228 ScratchReg = IsLP64 ? X86::RSP : X86::ESP; in adjustForSegmentedStacks()
3265 ScratchReg = X86::ESP; in adjustForSegmentedStacks()
3268 .addReg(X86::ESP) in adjustForSegmentedStacks()
3555 SPReg = X86::ESP; in adjustForHiPEPrologue()
3862 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP), in restoreWin32EHStackPointers()
H A DX86InstrCompiler.td29 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP],
34 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
39 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
123 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
151 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
463 // All calls clobber the non-callee saved registers. ESP is marked as
471 usesCustomInserter = 1, Uses = [ESP, SSP] in {
515 Uses = [ESP, SSP],
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
H A DX86MCTargetDesc.cpp200 {codeview::RegisterId::ESP, X86::ESP}, in initLLVMToSEHAndCVRegMapping()
468 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
786 #define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R) in getX86SubSuperRegister()
888 SP_SUB_SUPER(ESP) in getX86SubSuperRegister()
H A DX86WinCOFFTargetStreamer.cpp302 case X86::ESP: OS << "$esp"; break; in printFPOReg()
/freebsd-14.2/stand/i386/btx/btx/
H A Dbtx.S59 .set TSS_ESP0,0x4 # PL 0 ESP
214 pushl %eax # Set ESP
362 except.2: pushl 0x50(%esp,1) # Set ESP
497 addl -0x4(%esi),%ebx # User ESP
/freebsd-14.2/cddl/contrib/opensolaris/lib/libdtrace/i386/
H A Dregs.sed.in51 SED_REPLACE(ESP)
H A Dregs.d.in44 inline int R_ESP = @ESP@;
/freebsd-14.2/share/doc/IPv6/
H A DIMPLEMENTATION72 4.3 AH and ESP handling
1783 (3) AH, ESP and IPComp handling in kernel
1816 IP AH ESP IP payload
1819 implementation proposes it as "AH tunnel and ESP tunnel".
1827 4.3 AH and ESP handling
1832 Policy Database) is found. If ESP/AH is needed,
1838 safe to strip off the ESP/AH header on packet reception, since we
1908 alone, without AH/ESP.
1943 old IPsec ESP
1957 new IPsec ESP
[all …]
/freebsd-14.2/sys/amd64/amd64/
H A Dbpf_jit_machdep.h61 #define ESP 4 macro
/freebsd-14.2/lib/libc/net/
H A Dprotocols59 esp 50 ESP # encapsulating security payload

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