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Searched refs:ECC (Results 1 – 25 of 139) sorted by relevance

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/freebsd-14.2/crypto/openssl/test/recipes/30-test_evp_data/
H A Devppkey_kas.txt38 PrivPubKeyPair = KAS-ECC-CDH_P-192_C0:KAS-ECC-CDH_P-192_C0-PUBLIC
72 PrivPubKeyPair = KAS-ECC-CDH_P-192_C1:KAS-ECC-CDH_P-192_C1-PUBLIC
101 PrivPubKeyPair = KAS-ECC-CDH_P-192_C2:KAS-ECC-CDH_P-192_C2-PUBLIC
130 PrivPubKeyPair = KAS-ECC-CDH_P-192_C3:KAS-ECC-CDH_P-192_C3-PUBLIC
159 PrivPubKeyPair = KAS-ECC-CDH_P-192_C4:KAS-ECC-CDH_P-192_C4-PUBLIC
188 PrivPubKeyPair = KAS-ECC-CDH_P-192_C5:KAS-ECC-CDH_P-192_C5-PUBLIC
217 PrivPubKeyPair = KAS-ECC-CDH_P-192_C6:KAS-ECC-CDH_P-192_C6-PUBLIC
246 PrivPubKeyPair = KAS-ECC-CDH_P-192_C7:KAS-ECC-CDH_P-192_C7-PUBLIC
275 PrivPubKeyPair = KAS-ECC-CDH_P-192_C8:KAS-ECC-CDH_P-192_C8-PUBLIC
303 PrivPubKeyPair = KAS-ECC-CDH_P-192_C9:KAS-ECC-CDH_P-192_C9-PUBLIC
[all …]
H A Devppkey_ecc.txt56 # ECC CDH Alice with Bob peer
63 # ECC CDH Bob with Alice peer
76 # ECC CDH Bob with Malice peer
134 # ECC CDH Alice with Bob peer
141 # ECC CDH Bob with Alice peer
154 # ECC CDH Bob with Malice peer
212 # ECC CDH Alice with Bob peer
219 # ECC CDH Bob with Alice peer
290 # ECC CDH Alice with Bob peer
297 # ECC CDH Bob with Alice peer
[all …]
H A Devppkey_mismatch.txt34 PublicKey=KAS-ECC-CDH_K-163_C0-PUBLIC
81 PrivPubKeyPair = RSA-2048:KAS-ECC-CDH_K-163_C0-PUBLIC
84 PrivPubKeyPair = Alice-25519:KAS-ECC-CDH_K-163_C0-PUBLIC
/freebsd-14.2/sys/contrib/device-tree/Bindings/edac/
H A Dsocfpga-eccmgr.txt1 Altera SoCFPGA ECC Manager
15 L2 Cache ECC
22 On Chip RAM ECC
71 L2 Cache ECC
93 NAND FIFO ECC
101 DMA FIFO ECC
109 USB FIFO ECC
117 QSPI FIFO ECC
256 SDRAM ECC
282 DMA FIFO ECC
[all …]
H A Daspeed-sdram-edac.txt3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
10 Note, the bootloader must configure ECC mode in the memory controller.
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys.txt3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
9 These both ECC controllers correct single bit ECC errors and detect double bit
10 ECC errors.
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
H A Dsynopsys,ddrc-ecc.yaml15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
18 The Zynq DDR ECC controller has an optional ECC support in half-bus width
21 These both ECC controllers correct single bit ECC errors and detect double bit
22 ECC errors.
H A Dxlnx,zynq-ddrc-a05.yaml15 The Zynq DDR ECC controller has an optional ECC support in half-bus width
16 (16-bit) configuration. It is cappable of correcting single bit ECC errors
17 and detecting double bit ECC errors.
H A Dsnps,dw-umctl2-ddrc.yaml17 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
21 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
38 ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,
49 - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
52 - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
H A Dxlnx,zynqmp-ocmc-1.0.yaml14 The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
16 being written, the ECC is generated and written into the ECC RAM along with
/freebsd-14.2/sys/contrib/device-tree/Bindings/mtd/
H A Dnand-chip.yaml27 A phandle on the hardware ECC engine if any. There are
29 1/ The ECC engine is part of the NAND controller, in this
31 2/ The ECC engine is part of the NAND part (on-die), in this
33 3/ The ECC engine is external, in this case the phandle should
34 reference the specific ECC engine node.
38 description: Use a software ECC engine.
42 description: Do not use any ECC correction.
47 Desired ECC algorithm.
53 Maximum number of bits that can be corrected per ECC step.
59 Number of data bytes covered by a single ECC step.
H A Drockchip,nand-controller.yaml74 The ECC configurations that can be supported are as follows.
75 NFC v600 ECC 16, 24, 40, 60
78 NFC v622 ECC 16, 24, 40, 60
81 NFC v800 ECC 16
84 NFC v900 ECC 16, 40, 60, 70
95 The NFC driver need this information to select ECC
103 If specified it indicates that a different BCH/ECC setting is
105 NFC v600 ECC 16, 24
108 NFC v622 ECC 16, 24, 40, 60
111 NFC v800 ECC 16
[all …]
H A Dgpmc-nand.txt27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
105 How to select correct ECC scheme for your device ?
121 Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
124 helps in determining if given device can accommodate ECC syndrome:
129 ECC_BYTES number of ECC bytes generated to protect
138 Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
[all …]
H A Dnand-controller.yaml19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
63 Location of the ECC bytes. This location is unknown by default
64 but can be explicitly set to "oob", if all ECC bytes are
65 known to be stored in the OOB area, or "interleaved" if ECC
90 Whether or not the ECC strength should be maximized. The
91 maximum ECC strength is both controller and chip
92 dependent. The ECC engine has to select the ECC config
102 use this information to select ECC algorithms supported by
H A Dmtk-nand.txt5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
155 2) ECC Engine:
163 - reg: Base physical address and size of ECC.
164 - interrupts: Interrupts of ECC.
165 - clocks: ECC required clocks.
166 - clock-names: ECC clocks internal name.
H A Dmediatek,nand-ecc-engine.yaml7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
25 - description: Base physical address and size of ECC.
29 - description: ECC interrupt
H A Dnvidia-tegra20-nand.txt27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" ECC mode are: "rs", "bch".
32 per ECC step (always 512). Supported strength using HW ECC
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
H A Dgpmi-nand.txt32 - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
33 strength required. The required ECC strength is
39 ECC scheme.
51 per ECC step. Needs to be a multiple of 2.
53 that are covered by a single ECC step. The driver
H A Dhisi504-nand.txt17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
H A Dmarvell-nand.txt47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
49 not using hardware ECC. Howerver, it may be added when using hardware
50 ECC for clarification but will be ignored by the driver because ECC
59 patterns described in AN-379, "Marvell SoC NFC ECC".
/freebsd-14.2/sys/contrib/device-tree/Bindings/reserved-memory/
H A Dramoops.txt10 as kernel log messages, or for optional ECC error-correction data. The total
30 - ecc-size: enables ECC support and specifies ECC buffer size in bytes
31 (defaults to 0: no ECC)
/freebsd-14.2/secure/caroot/trusted/
H A DGlobalSign_ECC_Root_CA_-_R4.pem2 ## GlobalSign ECC Root CA - R4
20 Issuer: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
24 Subject: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
H A DCommScope_Public_Trust_ECC_Root-01.pem2 ## CommScope Public Trust ECC Root-01
20 Issuer: C = US, O = CommScope, CN = CommScope Public Trust ECC Root-01
24 Subject: C = US, O = CommScope, CN = CommScope Public Trust ECC Root-01
H A DAffirmTrust_Premium_ECC.pem2 ## AffirmTrust Premium ECC
19 Issuer: C = US, O = AffirmTrust, CN = AffirmTrust Premium ECC
23 Subject: C = US, O = AffirmTrust, CN = AffirmTrust Premium ECC
/freebsd-14.2/sys/contrib/device-tree/Bindings/arm/calxeda/
H A Dl2ecc.yaml7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.

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