Home
last modified time | relevance | path

Searched refs:DstVec (Results 1 – 5 of 5) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp496 Register DstVec = DstIsLeft ? Left : Right; in matchINS() local
505 MatchInfo = std::make_tuple(DstVec, DstLane, SrcVec, SrcLane); in matchINS()
515 Register DstVec, SrcVec; in applyINS() local
517 std::tie(DstVec, DstLane, SrcVec, SrcLane) = MatchInfo; in applyINS()
521 Builder.buildInsertVectorElement(Dst, DstVec, Extract, DstCst); in applyINS()
H A DAArch64InstructionSelector.cpp5948 Register DstVec = ScalarToVec->getOperand(0).getReg(); in selectBuildVector() local
5957 PrevMI = &*emitLaneInsert(std::nullopt, DstVec, I.getOperand(i).getReg(), in selectBuildVector()
5959 DstVec = PrevMI->getOperand(0).getReg(); in selectBuildVector()
5967 getRegClassForTypeOnBank(DstTy, *RBI.getRegBank(DstVec, MRI, TRI)); in selectBuildVector()
5987 MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {}).addReg(DstVec, 0, SubReg); in selectBuildVector()
/freebsd-14.2/contrib/llvm-project/llvm/lib/IR/
H A DVerifier.cpp3174 bool DstVec = DestTy->isVectorTy(); in visitUIToFPInst() local
3176 Check(SrcVec == DstVec, in visitUIToFPInst()
3183 if (SrcVec && DstVec) in visitUIToFPInst()
3197 bool DstVec = DestTy->isVectorTy(); in visitSIToFPInst() local
3199 Check(SrcVec == DstVec, in visitSIToFPInst()
3206 if (SrcVec && DstVec) in visitSIToFPInst()
3220 bool DstVec = DestTy->isVectorTy(); in visitFPToUIInst() local
3222 Check(SrcVec == DstVec, in visitFPToUIInst()
3228 if (SrcVec && DstVec) in visitFPToUIInst()
3244 Check(SrcVec == DstVec, in visitFPToSIInst()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp7555 SDValue DstVec; in LowerBUILD_VECTORvXi1() local
7562 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH); in LowerBUILD_VECTORvXi1()
7567 DstVec = DAG.getBitcast(VecVT, Imm); in LowerBUILD_VECTORvXi1()
7568 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
7572 DstVec = DAG.getUNDEF(VT); in LowerBUILD_VECTORvXi1()
7575 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerBUILD_VECTORvXi1()
7579 return DstVec; in LowerBUILD_VECTORvXi1()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12314 SDValue DstVec = DstIsLeft ? V1 : V2; in LowerVECTOR_SHUFFLE() local
12331 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()