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Searched refs:DstVT (Results 1 – 25 of 38) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1891 ValueType DstVT> {
1910 !if(!eq(DstVT.Size, 1),
1935 !if(!eq(DstVT.Size, 1),
1944 !if(!eq(DstVT.Size, 1),
2155 !if(!eq(DstVT.Size, 64),
2172 !if(!eq(DstVT.Size, 64),
2224 bit ret = !if(!eq(DstVT.Size, 64),
2252 field ValueType DstVT = ArgVT[0];
2324 field bit HasSDWAOMod = DstVT.isFP;
2414 HasModifiers, DstVT>.ret;
[all …]
H A DVOPInstructions.td1120 list<dag> ret3 = [(set P.DstVT:$vdst,
1125 list<dag> ret2 = [(set P.DstVT:$vdst,
1129 list<dag> ret1 = [(set P.DstVT:$vdst,
1145 list<dag> ret3 = [(set P.DstVT:$vdst,
1150 list<dag> ret2 = [(set P.DstVT:$vdst,
1155 list<dag> ret1 = [(set P.DstVT:$vdst,
1166 list<dag> ret3 = [(set P.DstVT:$vdst,
1171 list<dag> ret2 = [(set P.DstVT:$vdst,
1175 list<dag> ret1 = [(set P.DstVT:$vdst,
1184 list<dag> ret3 = [(set P.DstVT:$vdst,
[all …]
H A DVOP3PInstructions.td557 bit NoDstOverlap = !gt(DstVT.Size, 128);
564 let Src2VT = DstVT;
854 GCNPat < (P.DstVT (node
863 GCNPat < (P.DstVT (node
872 GCNPat < (P.DstVT (node
1297 (P.DstVT !setdagop(P.WmmaOutPat, !cast<Instruction>(Inst#"_twoaddr")))>;
1300 (P.DstVT !setdagop(P.WmmaInlineOutPat, !cast<Instruction>(Inst#"_threeaddr")))>;
1304 GCNPat <(P.DstVT !setdagop(P.SwmmacInPat, node)),
1305 (P.DstVT !setdagop(P.SwmmacOutPat, Inst))>;
1308 GCNPat <(P.DstVT !setdagop(P.SwmmacInPat, node)),
[all …]
H A DVOP1Instructions.td51 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
110 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
112 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
114 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP3Instructions.td109 let HasOMod = !ne(DstVT.Value, f16.Value);
958 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
959 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
960 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
H A DVOP2Instructions.td72 let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
132 [(set P.DstVT:$vdst,
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
467 0 /*Src2HasMods*/, DstVT>.ret;
930 (P.DstVT (op (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp1244 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1246 if (SrcVT != DstVT) { in X86SelectRet()
1534 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1552 if (DstVT == MVT::i64) { in X86SelectZExt()
1579 } else if (DstVT != MVT::i8) { in X86SelectZExt()
1592 if (!TLI.isTypeLegal(DstVT)) in X86SelectSExt()
1615 if (DstVT == MVT::i16) { in X86SelectSExt()
2517 if (DstVT != MVT::i8 && DstVT != MVT::i1) in X86SelectTrunc()
3680 if (DstVT.bitsGT(SrcVT)) in fastSelectInstruction()
3682 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
[all …]
H A DX86SelectionDAGInfo.cpp249 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
253 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp4155 MVT DstVT = VT; in getAVX512Node() local
9942 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
9945 DstVT = MVT::getVectorVT(DstVT, 128 / EltSizeInBits); in matchShuffleAsVTRUNC()
19708 (DstVT == MVT::f32 || DstVT == MVT::f64)) in LowerUINT_TO_FP()
20126 if (SrcVT == DstVT) in truncateVectorWithPACK()
21106 EVT TmpVT = DstVT; in LowerFP_TO_INT_SAT()
37134 DstVT = MVT::getVectorVT(DstVT, NumDstElts); in matchUnaryShuffle()
37429 DstVT = MaskVT; in matchBinaryShuffle()
42695 !(DstVT.isVector() && DstVT.getVectorElementType() == MVT::i1 && in combineCastedMaskArithmetic()
53579 EVT DstVT = in combineUIntToFP() local
[all …]
H A DX86ISelDAGToDAG.cpp1346 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1349 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1357 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1373 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1384 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1402 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1405 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1413 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1458 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
1469 assert(DstVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7228 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7232 (ins DstVT.FRC:$src1, SrcRC:$src),
7237 (ins DstVT.FRC:$src1, x86memop:$src),
7242 (ins DstVT.RC:$src1, SrcRC:$src2),
7244 [(set DstVT.RC:$dst,
7245 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
7251 [(set DstVT.RC:$dst,
7252 (OpNode (DstVT.VT DstVT.RC:$src1),
7270 [(set DstVT.RC:$dst,
7271 (OpNode (DstVT.VT DstVT.RC:$src1),
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1063 MVT DstVT; in SelectIToFP() local
1065 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1068 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1089 if (DstVT == MVT::f32) in SelectIToFP()
1112 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1134 if (DstVT == MVT::f32) in SelectIToFP()
1188 MVT DstVT, SrcVT; in SelectFPToI() local
1190 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1193 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1235 if (DstVT == MVT::i32) in SelectFPToI()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1458 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1460 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1461 !DstVT.isSimple()) in selectCast()
1466 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1478 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1496 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1502 if (SrcVT == DstVT) { in selectBitCast()
1508 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1863 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1864 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
H A DTargetLowering.cpp692 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
693 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
701 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
722 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
843 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
8034 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
8108 EVT DstVT = Node->getValueType(0); in expandFP_TO_UINT() local
8117 if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) || in expandFP_TO_UINT()
8213 EVT DstVT = Node->getValueType(0); in expandUINT_TO_FP() local
9294 EVT DstVT = LD->getValueType(0); in scalarizeVectorLoad() local
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h227 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3683 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3687 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3689 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3698 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3702 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
[all …]
H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1098 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1101 if (DstVT != MVT::i32) in selectFPToInt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1779 !DstVT.isInteger()) in isTruncateFree()
2745 if (!DstVT.isVector()) { in lowerFP_TO_INT_SAT()
2754 if (SatVT == DstVT) in lowerFP_TO_INT_SAT()
2764 Opc, DL, DstVT, Src, in lowerFP_TO_INT_SAT()
2791 MVT DstContainerVT = DstVT; in lowerFP_TO_INT_SAT()
2828 if (DstVT.isFixedLengthVector()) in lowerFP_TO_INT_SAT()
10636 DstVT = getContainerForFixedLengthVector(DstVT); in lowerVPFPIntConvOp()
10697 MVT InterimFVT = DstVT; in lowerVPFPIntConvOp()
10706 if (InterimFVT != DstVT) { in lowerVPFPIntConvOp()
13954 if (DstVT != XLenVT) in performFP_TO_INT_SATCombine()
[all …]
H A DRISCVISelLowering.h449 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
451 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2708 static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, in truncateVectorWithNARROW() argument
2713 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2720 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation"); in truncateVectorWithNARROW()
2721 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation"); in truncateVectorWithNARROW()
2742 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
2746 return DAG.getBitcast(DstVT, Res); in truncateVectorWithNARROW()
2756 return truncateVectorWithNARROW(DstVT, Res, DL, DAG); in truncateVectorWithNARROW()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1528 MVT DstVT; in SelectIToFP() local
1530 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1573 MVT DstVT; in SelectFPToI() local
1575 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp6187 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
6220 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
6241 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
6244 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
6248 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
6251 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
18551 EVT DstVT = N->getValueType(0); in PerformBITCASTCombine() local
19196 !DstVT.isInteger()) in isTruncateFree()
19199 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
20910 LC = RTLIB::getFPEXT(SrcVT, DstVT); in LowerFP_EXTEND()
[all …]
H A DARMISelLowering.h462 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1468 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1491 DstVT = MVT::i32; in tryIndexedLoad()
1495 if (DstVT == MVT::i64) in tryIndexedLoad()
1501 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1504 DstVT = MVT::i32; in tryIndexedLoad()
1508 if (DstVT == MVT::i64) in tryIndexedLoad()
1514 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1517 DstVT = MVT::i32; in tryIndexedLoad()
1538 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1474 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1477 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1482 if (SrcVT.bitsLT(DstVT)) in OptimizeNoopCopyExpression()
1491 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1493 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1496 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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