Searched refs:DstRegClass (Results 1 – 4 of 4) sorted by relevance
3054 unsigned DstRegClass; in buildRegSequence32() local3058 DstRegClass = AMDGPU::VReg_256RegClassID; in buildRegSequence32()3062 DstRegClass = AMDGPU::VReg_128RegClassID; in buildRegSequence32()3066 DstRegClass = AMDGPU::VReg_64RegClassID; in buildRegSequence32()3074 Ops.push_back(CurDAG->getTargetConstant(DstRegClass, DL, MVT::i32)); in buildRegSequence32()
3962 const TargetRegisterClass *DstRegClass; in buildRegSequence() local3965 DstRegClass = &AMDGPU::VReg_256RegClass; in buildRegSequence()3968 DstRegClass = &AMDGPU::VReg_128RegClass; in buildRegSequence()3971 DstRegClass = &AMDGPU::VReg_64RegClass; in buildRegSequence()3979 .addDef(MRI.createVirtualRegister(DstRegClass)); in buildRegSequence()
4638 const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg); in lowerWaveReduce() local4640 Register InitalValReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4642 Register AccumulatorReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4646 Register FF1Reg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()4647 Register LaneValueReg = MRI.createVirtualRegister(DstRegClass); in lowerWaveReduce()
3766 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem16Inst() local3768 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem16Inst()3893 int16_t DstRegClass = Desc.operands()[StartOp].RegClass; in expandMem9Inst() local3895 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID(); in expandMem9Inst()