Searched refs:DstInst (Results 1 – 4 of 4) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 446 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency() local
452 if (QII->canExecuteInBundle(*SrcInst, *DstInst) && in adjustSchedDependency()
460 if (DstInst->isCopy()) in adjustSchedDependency()
468 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
469 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency()
505 if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) && in adjustSchedDependency()
512 Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency); in adjustSchedDependency()
639 MachineInstr &DstInst = *Dst->getInstr(); in isBestZeroLatency() local
645 if (SrcInst.isPHI() || DstInst.isPHI()) in isBestZeroLatency()
648 if (!TII->isToBeScheduledASAP(SrcInst, DstInst) && in isBestZeroLatency()
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| H A D | HexagonSubtarget.h | 348 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MIRYamlMapping.h | 520 unsigned DstInst;
525 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
526 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
534 YamlIO.mapRequired("dstinst", Sub.DstInst);
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 453 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()
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