| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI() local
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo); in expandMI()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1584 Register DstHi; in applyMappingMAD_64_32() local
1591 DstHi = IsUnsigned ? B.buildUMulH(S32, Src0, Src1).getReg(0) in applyMappingMAD_64_32()
1593 MRI.setRegBank(DstHi, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1601 DstHi = IsUnsigned ? B.buildUMulH(S32, VSrc0, VSrc1).getReg(0) in applyMappingMAD_64_32()
1603 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1606 DstHi = buildReadFirstLane(B, MRI, DstHi); in applyMappingMAD_64_32()
1646 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1648 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1672 DstHi = AddHi.getReg(0); in applyMappingMAD_64_32()
1673 MRI.setRegBank(DstHi, DstBank); in applyMappingMAD_64_32()
[all …]
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| H A D | SIInstrInfo.cpp | 2130 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
2160 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
2182 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
2205 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
2212 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi) in expandPostRAPseudo()
2497 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
2501 DstHi) in expandPostRAPseudo()
2502 .addReg(DstHi); in expandPostRAPseudo()
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| H A D | AMDGPUInstructionSelector.cpp | 377 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
383 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD_SUB()
395 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi) in selectG_ADD_SUB()
409 .addReg(DstHi) in selectG_ADD_SUB()
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| H A D | SIISelLowering.cpp | 5053 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
5087 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in EmitInstrWithCustomInserter()
5097 .addReg(DstHi) in EmitInstrWithCustomInserter()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1852 auto DstHi = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
1901 MIRBuilder.buildExtract({DstHi}, {CASDst}, 64); in legalizeAtomicCmpxchg128()
1925 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
1936 MIRBuilder.buildMergeLikeInstr(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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| H A D | MipsSEInstrInfo.cpp | 718 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
720 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1948 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
1968 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
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