Searched refs:Dst0 (Results 1 – 5 of 5) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 877 [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) { in selectSuccBB() argument
878 return Prob.getEdgeProbability(&B, Dst0) < in selectSuccBB()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 383 MachineOperand &Dst0 = MI->getOperand(0); in updateOperand() local
385 assert(Dst0.isDef() && Dst1.isDef()); in updateOperand()
389 const TargetRegisterClass *Dst0RC = MRI->getRegClass(Dst0.getReg()); in updateOperand()
406 Dst0.setReg(NewReg0); in updateOperand()
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| H A D | AMDGPUInstructionSelector.cpp | 984 Register Dst0 = MI.getOperand(0).getReg(); in selectDivScale() local
987 LLT Ty = MRI->getType(Dst0); in selectDivScale()
1007 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) in selectDivScale()
2097 Register Dst0 = MI.getOperand(0).getReg(); in selectDSBvhStackIntrinsic() local
2108 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::DS_BVH_STACK_RTN_B32), Dst0) in selectDSBvhStackIntrinsic()
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| H A D | AMDGPURegisterBankInfo.cpp | 1562 Register Dst0 = MI.getOperand(0).getReg(); in applyMappingMAD_64_32() local
1691 B.buildMergeLikeInstr(Dst0, {DstLo, DstHi}); in applyMappingMAD_64_32()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 7453 auto [Dst0, Dst0Ty, Dst1, Dst1Ty, LHS, LHSTy, RHS, RHSTy] = in lowerSADDO_SSUBO()
7461 MIRBuilder.buildAdd(Dst0, LHS, RHS); in lowerSADDO_SSUBO()
7463 MIRBuilder.buildSub(Dst0, LHS, RHS); in lowerSADDO_SSUBO()
7476 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); in lowerSADDO_SSUBO()
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