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Searched refs:DestRC (Results 1 – 6 of 6) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
54 } else if (DestRC == &NVPTX::Float32RegsRegClass) { in copyPhysReg()
57 } else if (DestRC == &NVPTX::Float64RegsRegClass) { in copyPhysReg()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp373 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
378 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
381 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
585 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
595 if (DestRC != RC) { in ListScheduleBottomUp()
597 if (!DestRC && !NewDef) in ListScheduleBottomUp()
604 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
H A DScheduleDAGRRList.cpp1220 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1225 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1228 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1566 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1576 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1578 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1584 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp664 const TargetRegisterClass *DestRC = in runOnMachineFunction() local
666 Register NewDst = MRI->createVirtualRegister(DestRC); in runOnMachineFunction()
H A DSIFoldOperands.cpp844 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand() local
846 if (DestRC == &AMDGPU::AGPR_32RegClass && in foldOperand()
858 unsigned MovOp = TII->getMovOpcode(DestRC); in foldOperand()
H A DSIInstrInfo.cpp7675 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
7676 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
7921 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
7922 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
7965 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitXnor() local
7983 Register NewDest = MRI.createVirtualRegister(DestRC); in splitScalar64BitXnor()