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Searched refs:Dest0 (Results 1 – 4 of 4) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp53 Register Dest0, Register Dest1, Register Src0, in PairedCopy() argument
57 if (Dest0 == Src1 && Dest1 == Src0) { in PairedCopy()
59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
62 } else if (Dest0 != Src0 || Dest1 != Src1) { in PairedCopy()
63 if (Dest0 == Src1 || Dest1 != Src0) { in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1201 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair() local
1260 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeRead2Pair()
1389 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair() local
1393 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeImagePair()
1435 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSMemLoadImmPair() local
1439 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeSMemLoadImmPair()
1490 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair() local
1494 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeBufferLoadPair()
1549 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair() local
1553 .add(*Dest0) // Copy to same destination including flags and sub reg. in mergeTBufferLoadPair()
[all …]
H A DSIInstrInfo.cpp7101 MachineOperand &Dest0 = Inst.getOperand(0); in moveToVALUImpl() local
7110 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg())); in moveToVALUImpl()
7119 MRI.replaceRegWith(Dest0.getReg(), DestReg); in moveToVALUImpl()
H A DSIISelLowering.cpp4729 MachineOperand &Dest0 = MI.getOperand(0); in EmitInstrWithCustomInserter() local
4737 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1); in EmitInstrWithCustomInserter()