Searched refs:Demanded (Results 1 – 7 of 7) sorted by relevance
| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInsertVSETVLI.cpp | 1074 DemandedFields &Demanded) { in adjustIncoming() argument
1077 if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() && in adjustIncoming()
1082 Demanded.LMUL = true; in adjustIncoming()
1106 DemandedFields Demanded = getDemanded(MI, MRI, ST); in transferBefore() local
1107 const VSETVLIInfo IncomingInfo = adjustIncoming(PrevInfo, NewInfo, Demanded); in transferBefore()
1118 if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero)) in transferBefore()
1122 ((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info) in transferBefore()
1124 ((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(), in transferBefore()
1127 (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() || in transferBefore()
1129 (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() || in transferBefore()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | BDCE.cpp | 112 APInt Demanded = DB.getDemandedBits(SE); in bitTrackingDCE() local
116 if (Demanded.countl_zero() >= (DestBitSize - SrcBitSize)) { in bitTrackingDCE()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 37 const APInt &Demanded) { in ShrinkDemandedConstant() argument
48 if (C->isSubsetOf(Demanded)) in ShrinkDemandedConstant()
52 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded)); in ShrinkDemandedConstant()
1419 APInt Demanded, APInt &Undef) { in SimplifyDemandedVectorElts() argument
1422 if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) { in SimplifyDemandedVectorElts()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3680 APInt Demanded = APInt::getLowBitsSet(LHS.getValueSizeInBits(), 24); in simplifyMul24() local
3685 SDValue DemandedLHS = TLI.SimplifyMultipleUseDemandedBits(LHS, Demanded, DAG); in simplifyMul24()
3686 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG); in simplifyMul24()
3694 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24()
3696 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24()
5171 APInt Demanded = APInt::getBitsSet(32, in PerformDAGCombine() local
5179 if (TLI.ShrinkDemandedConstant(BitsFrom, Demanded, TLO) || in PerformDAGCombine()
5180 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20199 unsigned Demanded = DemandedBits.getZExtValue(); in targetShrinkDemandedConstant() local
20200 unsigned ShrunkMask = Mask & Demanded; in targetShrinkDemandedConstant()
20201 unsigned ExpandedMask = Mask | ~Demanded; in targetShrinkDemandedConstant()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1986 const APInt &Demanded, in optimizeLogicalImm() argument
1999 uint64_t DemandedBits = Demanded.getZExtValue(); in optimizeLogicalImm()
2054 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && in optimizeLogicalImm()
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 25653 APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; in visitVECTOR_SHUFFLE() local
25654 Demanded.setBit(M % NumElts); in visitVECTOR_SHUFFLE()
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