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Searched refs:DefaultMode (Results 1 – 12 of 12) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DInfoByHwMode.h39 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
51 if (AI != A.end() && AI->first == DefaultMode) { in union_modes()
55 if (BI != B.end() && BI->first == DefaultMode) { in union_modes()
85 Modes.push_back(DefaultMode); in union_modes()
113 return !Map.empty() && Map.begin()->first == DefaultMode; in hasDefault()
132 assert(F != Map.end() && F->first == DefaultMode); in get()
138 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
149 Map.insert(std::make_pair(DefaultMode, I)); in makeSimple()
159 ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); } in ValueTypeByHwMode()
H A DCodeGenHwModes.h46 enum : unsigned { DefaultMode = 0 }; enumerator
H A DInfoByHwMode.cpp26 if (Mode == DefaultMode) in getModeName()
71 if (D != Map.end() && D->first == DefaultMode) in getOrCreateTypeForMode()
H A DCodeGenHwModes.cpp86 return DefaultMode; in getHwModeId()
H A DRegisterBankEmitter.cpp266 if (M == DefaultMode) in emitBaseClassImplementation()
H A DCodeGenDAGPatterns.cpp134 if (DefaultMode == M) { in insert()
156 if (M == DefaultMode || hasMode(M)) in constrain()
158 Map.insert({M, Map.at(DefaultMode)}); in constrain()
862 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1798 if (S.get(DefaultMode).empty()) in setDefaultMode()
4456 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4471 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4473 AppendPattern(P, DefaultMode, DefaultCheck); in ExpandHwModeBasedTypes()
H A DCodeGenRegisters.cpp799 RSI.insertRegSizeForMode(DefaultMode, RI); in CodeGenRegisterClass()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td474 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
476 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
478 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
480 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
482 def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
484 def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
487 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
489 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
491 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
493 def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIModeRegister.cpp122 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon159a51cf0111::SIModeRegister
124 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td32 defvar LA32 = DefaultMode;
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td997 defvar RV32 = DefaultMode;
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td39 def DefaultMode : HwMode<"", []>;