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Searched refs:DefReg (Results 1 – 25 of 41) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp169 Register DefReg = Def.getReg(); in transferUsedLanes() local
170 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
204 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
205 if (!DefReg.isVirtual()) in transferDefinedLanesStep()
207 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
347 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
350 if (DefReg.isVirtual()) { in determineInitialUsedLanes()
433 Register DefReg = Def.getReg(); in isUndefInput() local
434 if (!DefReg.isVirtual()) in isUndefInput()
436 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in isUndefInput()
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H A DMachineSink.cpp378 Register DefReg; in PerformSinkAndFold() local
394 if (DefReg) in PerformSinkAndFold()
396 DefReg = Reg; in PerformSinkAndFold()
424 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in PerformSinkAndFold()
430 Worklist.push_back(DefReg); in PerformSinkAndFold()
556 Worklist.push_back(DefReg); in PerformSinkAndFold()
1914 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
1916 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
1949 for (unsigned DefReg : DefedRegsInCopy) in updateLiveIn() local
1950 for (MCPhysReg S : TRI->subregs_inclusive(DefReg)) in updateLiveIn()
H A DTailDuplicator.cpp352 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
365 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DImplicitNullChecks.cpp716 unsigned DefReg = NoRegister; in insertFaultingInstr() local
718 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
729 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DLiveVariables.cpp213 Register DefReg = MO.getReg(); in FindLastPartialDef() local
214 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
215 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg)) in FindLastPartialDef()
H A DPHIElimination.cpp202 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local
203 if (MRI->use_nodbg_empty(DefReg)) { in runOnMachineFunction()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h445 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
810 DefReg = DefSrcReg->Reg; in findValueFromDefImpl()
821 if (MO.getReg() == DefReg) in findValueFromDefImpl()
834 return DefReg; in findValueFromDefImpl()
879 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs() local
880 if (MRI.use_nodbg_empty(DefReg)) { in tryCombineUnmergeDefs()
894 MI.getOperand(DefIdx).setReg(DefReg); in tryCombineUnmergeDefs()
1189 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues() local
1191 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
1207 if (!MRI.use_empty(DefReg)) { in tryCombineUnmergeValues()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp473 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
474 if (!DefReg.isVirtual() || !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
476 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
477 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
640 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
654 DefDIs.updateReg(DefReg); in moveAndTeeForMultiUse()
668 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
669 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
913 Register DefReg = SubsequentDef->getReg(); in runOnMachineFunction() local
916 if (DefReg != UseReg || !MRI.hasOneNonDBGUse(DefReg)) in runOnMachineFunction()
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H A DWebAssemblyExplicitLocals.cpp192 for (auto DefReg : Def->defs()) { in findStartOfTree() local
193 if (!MFI.isVRegStackified(DefReg.getReg())) { in findStartOfTree()
300 Register DefReg = MI.getOperand(2).getReg(); in runOnMachineFunction() local
301 const TargetRegisterClass *RC = MRI.getRegClass(DefReg); in runOnMachineFunction()
304 if (!MFI.isVRegStackified(DefReg)) { in runOnMachineFunction()
305 unsigned LocalId = getLocalId(Reg2Local, MFI, CurLocal, DefReg); in runOnMachineFunction()
H A DWebAssemblyCFGStackify.cpp831 Register DefReg = MI.getOperand(2).getReg(); in unstackifyVRegsUsedInSplitBB() local
834 MFI.unstackifyVReg(DefReg); in unstackifyVRegsUsedInSplitBB()
836 WebAssembly::getCopyOpcodeForRegClass(MRI.getRegClass(DefReg)); in unstackifyVRegsUsedInSplitBB()
838 .addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
839 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRedundantCopyElimination.cpp120 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
123 if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) && in optimizeBlock()
124 TargetReg == DefReg) { in optimizeBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp381 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
384 if (!MRI->isReserved(DefReg) && in optimizeBlock()
388 if (KnownReg.Reg != DefReg && in optimizeBlock()
389 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
413 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) in optimizeBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp557 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
558 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
595 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
618 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
671 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
690 LLT Ty = MRI.getType(DefReg); in selectConstant()
860 Register DefReg = SrcReg; in selectZext() local
877 .addReg(DefReg) in selectZext()
1423 MRI.setRegBank(DefReg, RegBank); in selectMergeValues()
1437 DefReg = Tmp; in selectMergeValues()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.cpp178 auto DefReg = Inst.getOperand(I).getReg(); in updateState() local
179 if (isGPR(DefReg)) in updateState()
180 setGPRState(DefReg, std::nullopt); in updateState()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp673 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
679 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
745 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
785 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
787 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCPreEmitPeephole.cpp259 Register DefReg; in addLinkerOpt() member
291 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
292 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
301 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp368 int DefReg = 0; in loadImmediate() local
371 DefReg = MO.getReg(); in loadImmediate()
390 if (DefReg != Reg) { in loadImmediate()
405 if (DefReg!= SpReg) { in loadImmediate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp508 const Register DefReg = MI.getOperand(0).getReg(); in select() local
509 const LLT DefTy = MRI.getType(DefReg); in select()
512 MRI.getRegClassOrRegBank(DefReg); in select()
531 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
967 Register DefReg = MI.getOperand(0).getReg(); in selectAddr() local
968 const LLT DefTy = MRI.getType(DefReg); in selectAddr()
994 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
1022 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest}) in selectAddr()
1048 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {}) in selectAddr()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2298 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
2299 LLT Ty = MRI.getType(DefReg); in earlySelect()
2449 const LLT DefTy = MRI.getType(DefReg); in select()
2452 MRI.getRegClassOrRegBank(DefReg); in select()
2619 const LLT DefTy = MRI.getType(DefReg); in select()
2700 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3304 const LLT DstTy = MRI.getType(DefReg); in select()
3389 {DefReg}, {SrcReg}) in select()
5326 const LLT DstTy = MRI.getType(DefReg); in selectUSMovFromExtend()
6910 Register DefReg = MI.getOperand(0).getReg(); in isWorthFoldingIntoExtendedReg() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp592 Register DefReg = DefOp.getReg(); in buildClosure() local
593 if (!DefReg.isVirtual()) { in buildClosure()
597 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
H A DX86LoadValueInjectionLoadHardening.cpp369 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph() local
370 for (auto UseID : L.getAllReachedUses(DefReg, Def)) { in getGadgetGraph()
375 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1994 Register DefReg = Def.getReg(); in tryFoldLoad() local
1996 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
2001 for (const MachineInstr &I : MRI->use_nodbg_instructions(DefReg)) in tryFoldLoad()
2023 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in tryFoldLoad()
2024 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2026 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp214 Register DefReg = MODef.getReg(); in eraseInstrWithNoUses() local
215 if (!DefReg.isVirtual()) { in eraseInstrWithNoUses()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp177 static bool isRegUsedByPhiNodes(Register DefReg, in isRegUsedByPhiNodes() argument
180 if (P.second == DefReg) in isRegUsedByPhiNodes()
199 Register DefReg = findLocalRegDef(LocalMI); in flushLocalValueMap() local
200 if (!DefReg) in flushLocalValueMap()
202 if (FuncInfo.RegsWithFixups.count(DefReg)) in flushLocalValueMap()
204 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); in flushLocalValueMap()
205 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { in flushLocalValueMap()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp1044 unsigned DefReg = 0; in getUniqueDefVReg() local
1051 if (DefReg != 0) in getUniqueDefVReg()
1053 DefReg = R; in getUniqueDefVReg()
1055 return DefReg; in getUniqueDefVReg()

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