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Searched refs:DefRC (Results 1 – 17 of 17) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp384 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
389 if (DefRC == SrcRC) in shareSameRegisterFile()
395 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
403 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
408 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
411 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
414 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
419 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
H A DDetectDeadLanes.cpp289 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
303 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
H A DPeepholeOptimizer.cpp732 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
795 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1294 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1295 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
H A DRegisterCoalescer.cpp1342 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1354 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1390 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1482 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1484 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1486 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.h76 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
H A DX86RegisterInfo.cpp221 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
232 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
H A DX86SpeculativeLoadHardening.cpp1956 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
1961 Register UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp429 const TargetRegisterClass *DefRC = nullptr; in select() local
431 DefRC = TRI.getRegClass(DestReg); in select()
433 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
436 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h237 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
H A DARMBaseRegisterInfo.cpp936 bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
941 if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 && in shouldRewriteCopySrc()
946 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp514 const TargetRegisterClass *DefRC = in select() local
516 if (!DefRC) { in select()
523 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
524 if (!DefRC) { in select()
531 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h270 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
H A DAMDGPUInstructionSelector.cpp227 const TargetRegisterClass *DefRC in selectPHI() local
229 if (!DefRC) { in selectPHI()
236 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB); in selectPHI()
237 if (!DefRC) { in selectPHI()
245 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
H A DSIRegisterInfo.cpp2917 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
2937 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h631 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1952 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1953 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1954 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2454 const TargetRegisterClass *DefRC in select() local
2456 if (!DefRC) { in select()
2462 DefRC = getRegClassForTypeOnBank(DefTy, RB); in select()
2463 if (!DefRC) { in select()
2471 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()